Is there any specific way of coding [either in VHDL or Verilog]a Latch (any type of latch ), but the tool is forced to infer a clock buffer (..in other words, treat the signal which would be input to the clock buffer as clock pin) for the signal connecting to the GATE (G) input of the latch. The component should still behave like a latch and not as flop.
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Is there any specific way of coding
- Thread starter RVSachin
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