Initializing a RAM

[fatmosh]

My program has the need to intitialize an instance of a RAM on startup, before doing the actual algorithm. I am unsure of how exactly to do this. I have created a ram.vhd file which contains an array of 256 bytes. On startup, I need to put "0" in block zero, "1" in block 1, ..., "255" in block 255. The way I tried to do it was:

state: ram port map(clk, state_addr, state_data_in, state_data_out, state_we);

...

for count in 0 to 255 loop
wait until clk'event and clk = '1';
state_addr <= to_unsigned(count, 8);
state_data_in <= to_unsigned(count, 8);
state_we <= '1';
end loop;

Which I thought would write to the RAM every clock cycle for 256 clock cycles.

However, this will not properly synthesize. I get the error: ERROR:Xst:825 - *file*.vhd line 154: Wait statement in a procedure is not accepted.

Is there a better way to do this that I'm just not thinking of?

Thanks for any insight

 

[VHDLguy]

You cannot put you clock wait statement in a loop like that.

There can only be one wait statement (or clock'event) per process, you have effectively created 256 of them. If what you wrote was valid, and I guess from a simulation point of view it is, the result would be 256 clocks per run of the process.

a better way to do it would be:

signal count : unsigned(7 downto 0);

...

INIT_PROC : process(clk, reset)
begin
if reset = '1' then
count <= (others => '0');
state_addr <= (others => '0');
state_data_in <= (others => '0');
state_we <= '0';
init <= '1';
elsif (clk'event and clk = '1') then
if init = '1' then
-- note that count will wrap to 0 at the end, so 0 will be the last
-- RAM location to be cleared.
count <= count + 1;
state_addr <= count;
state_data_in <= count;
state_we <= '1';
if count = "11111111" then
init <= '0';
end if;
else
-- now do you normal RAM access

end if;
end if;
end process;


You will note that I added the init signal. The reason being is that you will also need to access the RAM for your normal operation, and unless you plan on having a different signal and then MUX'ing the init and normal signals, then you will have to do it in the same process. Even if you do plan on MUX'ing it, you will still need some signal to switch that mux, so the init signal would be good for that. The difference then is that you could do you normal operation from a different process, possibly a good thing.

--

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