Initialization

[avib]

Hi,
I'm using Altera's Acex device and I have a problem:
My design don't use reset signal so I can't initialize the internal signals and
registers. when I simulate it I don't have any problem (because I initialize
the signals when I declare them) but when I Synthesize it (Synplicity) and
then use the place and route tool (Quartus) the signals are being ignored
Does anybody know how can I solve this problem?
thanks,
Avi

 

Hi AVI,

Please note that initializing signals to some values is merely a simulation issue and they are ignored by synthesis tools. So, when the RTL level is simulated, it looks fine, but when the gate-level netlist is simulated, you might find that the outputs are unassigned for the starting few cycles, but normal thereafter. This can be ignored safely.