Hello, I am having this problem, hope someone could help me.
Below is a portion of VHDL file. I faced the problem of storing values into arrays through indexing. Currently I am using Altera Max Plus II. And the error is:
"Bounds of non-constant array reaches beyond the bounds of the array"
I could not figure out what could have prompted this error.
************************************************
The Package used is:
PACKAGE array_consequent IS
constant rules_width : INTEGER :=25;
TYPE result_consq IS ARRAY (1 to rules_width) of std_logic_vector(3 downto 0);
END array_consequent;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY work;
USE work.array_consequent.all; --containts the number of rules
ARCHITECTURE loading OF ctrlblck IS
SIGNAL result: result_consq;
SIGNAL NM,NS,Z,PS,PM: STD_LOGIC_VECTOR(3 downto 0);
SIGNAL Count1:INTEGER;
BEGIN
dummyROCESS(Clock)
BEGIN
IF Clock='1' THEN
IF Count1<rules_width THEN
Count1<=Count1+1;
ELSE
Count1<=1;
END IF;
END IF;
END PROCESS DUMMY;
loadingrulesROCESS(Count1)
BEGIN
IF Data_In="0000" THEN
result(Count1) <= "0000";
ELSIF Data_In="0001" THEN
result(Count1) <= NM;
ELSIF Data_In="0010" THEN
result(Count1) <= NS;
ELSIF Data_In="0011" THEN
result(Count1) <= Z;
ELSIF Data_In="0100" THEN
result(Count1) <= PS;
ELSIF Data_In="0101" THEN
result(Count1) <= PM;
ELSE
result(Count1) <= "0000";
END IF;
END PROCESS loadingrules;
END loading;
Below is a portion of VHDL file. I faced the problem of storing values into arrays through indexing. Currently I am using Altera Max Plus II. And the error is:
"Bounds of non-constant array reaches beyond the bounds of the array"
I could not figure out what could have prompted this error.
************************************************
The Package used is:
PACKAGE array_consequent IS
constant rules_width : INTEGER :=25;
TYPE result_consq IS ARRAY (1 to rules_width) of std_logic_vector(3 downto 0);
END array_consequent;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY work;
USE work.array_consequent.all; --containts the number of rules
ARCHITECTURE loading OF ctrlblck IS
SIGNAL result: result_consq;
SIGNAL NM,NS,Z,PS,PM: STD_LOGIC_VECTOR(3 downto 0);
SIGNAL Count1:INTEGER;
BEGIN
dummyROCESS(Clock)
BEGIN
IF Clock='1' THEN
IF Count1<rules_width THEN
Count1<=Count1+1;
ELSE
Count1<=1;
END IF;
END IF;
END PROCESS DUMMY;
loadingrulesROCESS(Count1)
BEGIN
IF Data_In="0000" THEN
result(Count1) <= "0000";
ELSIF Data_In="0001" THEN
result(Count1) <= NM;
ELSIF Data_In="0010" THEN
result(Count1) <= NS;
ELSIF Data_In="0011" THEN
result(Count1) <= Z;
ELSIF Data_In="0100" THEN
result(Count1) <= PS;
ELSIF Data_In="0101" THEN
result(Count1) <= PM;
ELSE
result(Count1) <= "0000";
END IF;
END PROCESS loadingrules;
END loading;