here is the code for the reciever:
1: library IEEE;
2: use IEEE.std_logic_1164.all;
3:
4: entity PRBS_RX is
5: port(
6: CLK: in STD_LOGIC;
7: EN_PRBSRX: in STD_LOGIC;
8: PRBS_IN: in STD_LOGIC;
9: RST_PRBS: in STD_LOGIC;
10: READ_PRBS_IN_TEST: out STD_LOGIC;
11: PRBS_ERROR: out STD_LOGIC;
12: );
13: end PRBS_RX;
14:
15: architecture PRBS_RX_arch of PRBS_RX is
16:
17: signal MUX_OUT: STD_LOGIC;
18: signal PRBS_FEEDBACK: STD_LOGIC;
19: signal READ_PRBS_IN: STD_LOGIC;
20: signal Q: STD_LOGIC_VECTOR(14 downto 0);
21: signal D: STD_LOGIC_VECTOR(14 downto 0);
22: signal COUNTPRBS: INTEGER range 0 to 31;
23: signal PRBS_OUT: STD_LOGIC;
24:
25:
26: begin
27:
28: process(CLK, EN_PRBSRX, RST_PRBS)
29: begin
30: if(CLK'event and CLK = '1')then
31: if(RST_PRBS = '1')then
32: Q <= "000000000000000";
33: else
34: if(EN_PRBSRX = '1')then
35: Q <= D;
36: else
37: Q <= Q;
38: end if;
39: end if;
40: end if;
41: end process;
42:
43:
44: process(PRBS_FEEDBACK, READ_PRBS_IN, PRBS_IN, PRBS_FEEDBACK)
45: begin
46: if(READ_PRBS_IN = '0')then
47: MUX_OUT <= PRBS_IN;
48: else
49: MUX_OUT <= PRBS_FEEDBACK;
50: endif;
51: end process;
52:
53:
54: process(CLK, RST_PRBS, EN_PRBSRX)
55: begin
56: if(CLK'event and CLK = '1')then
57: if(RST_PRBS = '1' or COUNTPRBS = 31)then
58: COUNTPRBS <= 0;
59: elsif(EN_PRBSRX = '1')then
60: COUNTPRBS <= COUNTPRBS + 1;
61: else
62: COUNTPRBS <= COUNTPRBS;
63: endif;
64: endif;
65: end process;
66:
67:
68: process(CLK, COUNTPRBS, RST_PRBS, EN_PRBSRX)
69: begin
70:
71: if(CLK'event and CLK = '1')then
72: if(RST_PRBS = '1')then
73: READ_PRBS_IN <= '0';
74: elsif(COUNTPRBS = 31)then
75: READ_PRBS_IN <= '1';
76: endif;
77: endif;
78: end process;
79:
80:
81: process(CLK, PRBS_FEEDBACK, PRBS_IN, READ_PRBS_IN)
82: begin
83: if(CLK'event and CLK = '1')then
84: if(READ_PRBS_IN = '1')then
85: PRBS_ERROR <= (PRBS_FEEDBACK xnor PRBS_IN);
86: else
87: PRBS_ERROR <= '0';
88: endif;
89: endif;
90: end process;
91:
92:
93: D(14) <= MUX_OUT;
94: D(13) <= Q(14);
95: D(12) <= Q(13);
96: D(11) <= Q(12);
97: D(10) <= Q(11);
98: D(9) <= Q(10);
99: D(8) <= Q(9);
100: D(7) <= Q(8);
101: D(6) <= Q(7);
102: D(5) <= Q(6);
103: D(4) <= Q(5);
104: D(3) <= Q(4);
105: D(2) <= Q(3);
106: D(1) <= Q(2);
107: D(0) <= Q(1);
108: PRBS_FEEDBACK <= (Q(0) xor Q(1));
109:
110: READ_PRBS_IN_TEST <= READ_PRBS_IN; --for test purposes only--
111:
112: end PRBS_RX_arch;
i NEED TO SET UP THE TEST BENCH CODE FOR IT. aNY HELP WILL BE APPRECIATED.
1: library IEEE;
2: use IEEE.std_logic_1164.all;
3:
4: entity PRBS_RX is
5: port(
6: CLK: in STD_LOGIC;
7: EN_PRBSRX: in STD_LOGIC;
8: PRBS_IN: in STD_LOGIC;
9: RST_PRBS: in STD_LOGIC;
10: READ_PRBS_IN_TEST: out STD_LOGIC;
11: PRBS_ERROR: out STD_LOGIC;
12: );
13: end PRBS_RX;
14:
15: architecture PRBS_RX_arch of PRBS_RX is
16:
17: signal MUX_OUT: STD_LOGIC;
18: signal PRBS_FEEDBACK: STD_LOGIC;
19: signal READ_PRBS_IN: STD_LOGIC;
20: signal Q: STD_LOGIC_VECTOR(14 downto 0);
21: signal D: STD_LOGIC_VECTOR(14 downto 0);
22: signal COUNTPRBS: INTEGER range 0 to 31;
23: signal PRBS_OUT: STD_LOGIC;
24:
25:
26: begin
27:
28: process(CLK, EN_PRBSRX, RST_PRBS)
29: begin
30: if(CLK'event and CLK = '1')then
31: if(RST_PRBS = '1')then
32: Q <= "000000000000000";
33: else
34: if(EN_PRBSRX = '1')then
35: Q <= D;
36: else
37: Q <= Q;
38: end if;
39: end if;
40: end if;
41: end process;
42:
43:
44: process(PRBS_FEEDBACK, READ_PRBS_IN, PRBS_IN, PRBS_FEEDBACK)
45: begin
46: if(READ_PRBS_IN = '0')then
47: MUX_OUT <= PRBS_IN;
48: else
49: MUX_OUT <= PRBS_FEEDBACK;
50: endif;
51: end process;
52:
53:
54: process(CLK, RST_PRBS, EN_PRBSRX)
55: begin
56: if(CLK'event and CLK = '1')then
57: if(RST_PRBS = '1' or COUNTPRBS = 31)then
58: COUNTPRBS <= 0;
59: elsif(EN_PRBSRX = '1')then
60: COUNTPRBS <= COUNTPRBS + 1;
61: else
62: COUNTPRBS <= COUNTPRBS;
63: endif;
64: endif;
65: end process;
66:
67:
68: process(CLK, COUNTPRBS, RST_PRBS, EN_PRBSRX)
69: begin
70:
71: if(CLK'event and CLK = '1')then
72: if(RST_PRBS = '1')then
73: READ_PRBS_IN <= '0';
74: elsif(COUNTPRBS = 31)then
75: READ_PRBS_IN <= '1';
76: endif;
77: endif;
78: end process;
79:
80:
81: process(CLK, PRBS_FEEDBACK, PRBS_IN, READ_PRBS_IN)
82: begin
83: if(CLK'event and CLK = '1')then
84: if(READ_PRBS_IN = '1')then
85: PRBS_ERROR <= (PRBS_FEEDBACK xnor PRBS_IN);
86: else
87: PRBS_ERROR <= '0';
88: endif;
89: endif;
90: end process;
91:
92:
93: D(14) <= MUX_OUT;
94: D(13) <= Q(14);
95: D(12) <= Q(13);
96: D(11) <= Q(12);
97: D(10) <= Q(11);
98: D(9) <= Q(10);
99: D(8) <= Q(9);
100: D(7) <= Q(8);
101: D(6) <= Q(7);
102: D(5) <= Q(6);
103: D(4) <= Q(5);
104: D(3) <= Q(4);
105: D(2) <= Q(3);
106: D(1) <= Q(2);
107: D(0) <= Q(1);
108: PRBS_FEEDBACK <= (Q(0) xor Q(1));
109:
110: READ_PRBS_IN_TEST <= READ_PRBS_IN; --for test purposes only--
111:
112: end PRBS_RX_arch;
i NEED TO SET UP THE TEST BENCH CODE FOR IT. aNY HELP WILL BE APPRECIATED.