if generate statement 1

[naraic]

I have the following in my code:

OUTPUT: if ND = '1' and RDY = '0' generate
begin
DOUT0 <= (&quot;00&quot; & DIN0) + (&quot;00&quot; & DIN7) - &quot;0100000000&quot;;
end generate OUTPUT;[\code]

However, when ND and RDY are the appropriate values, the statement doesn't execute.

Any suggestions would be appreciated.

 

[jezwold]

Its difficult to say without seeing the context,what are the types and ranges of the signals.
I assume it compiles without any errors.

 

[naraic]

	OUTPUT: if ND = '1' generate
	begin
		DOUT0 <= (&quot;00&quot; & DIN0) + (&quot;00&quot; & DIN7) - &quot;0100000000&quot;; 
		DOUT1 <= (&quot;00&quot; & DIN1) + (&quot;00&quot; & DIN6) - &quot;0100000000&quot;;
		DOUT2 <= (&quot;00&quot; & DIN2) + (&quot;00&quot; & DIN5) - &quot;0100000000&quot;;
		DOUT3 <= (&quot;00&quot; & DIN3) + (&quot;00&quot; & DIN4) - &quot;0100000000&quot;;
		DOUT4 <= (&quot;00&quot; & DIN3) - (&quot;00&quot; & DIN4);
		DOUT5 <= (&quot;00&quot; & DIN2) - (&quot;00&quot; & DIN5);
		DOUT6 <= (&quot;00&quot; & DIN1) - (&quot;00&quot; & DIN6);
		DOUT7 <= (&quot;00&quot; & DIN0) - (&quot;00&quot; & DIN7);
	end generate OUTPUT;

ND is a std_logic input signal, DINx are std_logic vector(7 downto 0), and DOUTx are std_logic vector(9 downto 0) outputs. When ND goes from '0' to '1' however, there is no change in the DOUTx. Why is the generae statement not working? DOUTx is not driven anywhere else in the code.

 

[senjed]

I'm not so familiar with VHDL for modeling, but I'm sure your code is wrong for synthesis. In synthesis, the if-generate statement must have a condition which is computable for the simulator/synthesizer. In fact it should not contain a condition based on a signal. usually the If-generate statements are used in for-generate loops, and the condition is based on the loop variable
about you code, you could easily do the job in a process:
process(ND)
begin
if ND='1' then
DOUT0 <= (&quot;00&quot; & DIN0) + (&quot;00&quot; & DIN7) - &quot;0100000000&quot;;
DOUT1 <= (&quot;00&quot; & DIN1) + (&quot;00&quot; & DIN6) - &quot;0100000000&quot;;
DOUT2 <= (&quot;00&quot; & DIN2) + (&quot;00&quot; & DIN5) - &quot;0100000000&quot;;
DOUT3 <= (&quot;00&quot; & DIN3) + (&quot;00&quot; & DIN4) - &quot;0100000000&quot;;
DOUT4 <= (&quot;00&quot; & DIN3) - (&quot;00&quot; & DIN4);
DOUT5 <= (&quot;00&quot; & DIN2) - (&quot;00&quot; & DIN5);
DOUT6 <= (&quot;00&quot; & DIN1) - (&quot;00&quot; & DIN6);
DOUT7 <= (&quot;00&quot; & DIN0) - (&quot;00&quot; & DIN7);
end if;
of course it introduces latches. if you want to avoid it, use a clock signal to do it, or have a default value (for example (others => '0')) for all DOUTx signals. this deafault value would be placed before the if statement and the process will be implemented as MUXes

 

[naraic]

Thanks senjed