I need help with Altera Quartus 2 and VHDL please!!!!!. can anyone

[shirlarn]

hi all,
I desperately need some help with my vhdl code. I am working on a project with vhdl. Its AES secuity algorithm on a FPGA. I am trying to compile my code using Altera Quartus 2 .But experience errors likeError: VHDL type mismatch error at aes128_fast.vhd(124): type of indexed object that is assigned or mapped to target object must match target object type std_ulogic. there are other declaration errors like this. thought i change the type its giving some other errors. If anyone have experience in compiling the vhdl design in Altera Quartus2 .please let me know . Ican explain the problem in detail.
I need help please

 

[jeandelfrigo]

Shirlarn,

The problems you are encountering have nothing to do with Altera Quartus software, you would have the same problems ( maybe other formulation) with say a Xilinx tool or some other tool.

You need to check if the types are compatible or not ,when you are trying to assign a signal to another.
And you need to check if you have no index violations when using vectors. Some examples.

Assigning a std_logic to a std_logic_vector does not work default.

vector1 <= singleBit; will no work
vector1(?) <= singleBit; will work

vector1 : std_logic_vector(11 downto 0);
vector2 : std_logic_vector(4 downto 0);

vector1 <= vector2; will not work
vector1(11 downto 7) <= vector2; will work

vector1 : std_logic_vector(7 downto 0);
number1 : integer;

vector1 <= number1; will not work
vector1 <= conversionFunction(number1,X); will work

The problems you are encountering are VHDL coding and syntax errors, they are independant from tool and vendor.

I suggest you search for some VHDL syntax and type information on the net, because

a) you need to know this stuff, its a basic need for using VHDL

b) It impossible to post a complete guide on this forum

best regards

jeandelfrigo