VHDL124
Technical User
- Apr 27, 2008
- 1
1 Write VHDL code to implement an 8-bit one/zero/complement circuit. This circuit should have two select inputs S1,S0, eight data inputs X1,…,X8, and eight data outputs Y1,…,Y8. The outputs Y1,…,Y8, should be all 0s, all 1s, and the complements of X1,…,X8, respectively when S1S0=00,01,(10,11).
2 Write VHDL code to implement a 3-input 3-bit multiplexer. The select inputs are S0-S1, the data inputs are A2-A0, B2-B0, C2-C0, and the data outputs are Y2-Y0. The outputs Y2-Y0 should be equal to A2-A0,B2-B0,C2-C0 for the select-input combinations 00,01,10, respectively and should be zero when the select inputs are 11.
3 Indicate how the VHDL program in the above question must be modified if the Y outputs are floating when the select inputs are 11.
4 Determine logic expressions for the seven outputs of the seven-segment decoder. Use these expressions in a VHDL code to implement the device.
5 Design a 2-bit ALU to perform addition or subtraction. The two input numbers have two bits, denoted by [A1,A0], and [B1,B0]. The output bits include Y1,Y0, representing either sum or difference, plus a carry or borrow bit C. Another input S is used to select an operation: if S=1, addition will be performed, and if S=0, subtraction will be performed.
In this question, you are required to (1) draw the truth table according to the problem description; (2) determine simplified expressions for 3 output bits, in terms of 5 input bits;
and (3) write a VHDL program to implement the ALU.
2 Write VHDL code to implement a 3-input 3-bit multiplexer. The select inputs are S0-S1, the data inputs are A2-A0, B2-B0, C2-C0, and the data outputs are Y2-Y0. The outputs Y2-Y0 should be equal to A2-A0,B2-B0,C2-C0 for the select-input combinations 00,01,10, respectively and should be zero when the select inputs are 11.
3 Indicate how the VHDL program in the above question must be modified if the Y outputs are floating when the select inputs are 11.
4 Determine logic expressions for the seven outputs of the seven-segment decoder. Use these expressions in a VHDL code to implement the device.
5 Design a 2-bit ALU to perform addition or subtraction. The two input numbers have two bits, denoted by [A1,A0], and [B1,B0]. The output bits include Y1,Y0, representing either sum or difference, plus a carry or borrow bit C. Another input S is used to select an operation: if S=1, addition will be performed, and if S=0, subtraction will be performed.
In this question, you are required to (1) draw the truth table according to the problem description; (2) determine simplified expressions for 3 output bits, in terms of 5 input bits;
and (3) write a VHDL program to implement the ALU.