Dear all,
I am a beginning learner of VHDL. My following simple code got compile error, but I have no idea at all... Can anyone tell me what's wrong with it? The compile error message is also attached. Thanks a lot!!!
Peggy
entity bt_vertex is
port (A: in character; B,C: out character);
end bt_vertex;
architecture bt_vertex_arch of bt_vertex is
signal value: character := NUL;
begin
if value = NUL then
value <= A;
elsif A < value then
B <= A;
else
C <= A;
end if;
end bt_vertex_arch;
rror: CSVHDL0002: bt.vhdl: (line 9): Syntax error at or near `if'
Error: CSVHDL0002: bt.vhdl: (line 9): Invalid prefix for an indexed/selected/slice/attribute name
I am a beginning learner of VHDL. My following simple code got compile error, but I have no idea at all... Can anyone tell me what's wrong with it? The compile error message is also attached. Thanks a lot!!!
Peggy
entity bt_vertex is
port (A: in character; B,C: out character);
end bt_vertex;
architecture bt_vertex_arch of bt_vertex is
signal value: character := NUL;
begin
if value = NUL then
value <= A;
elsif A < value then
B <= A;
else
C <= A;
end if;
end bt_vertex_arch;
rror: CSVHDL0002: bt.vhdl: (line 9): Syntax error at or near `if'
Error: CSVHDL0002: bt.vhdl: (line 9): Invalid prefix for an indexed/selected/slice/attribute name
