how to make division synthesizable in a case statement?? pls help

[vampirebat83]

i have two 8 bit std_logic_vector inputs and one 16 bit std_logic_vector output
eg.
aluout <= data/accum;

this statement is within a case statement and i know that it is not syntesizable and i met with an error called operator arugement mismatch.. so i tried using a function call to just perform this division operation but the error is still there.. i am at wits end as i am only a beginner to VHDL.. so please help.. thanks

 

[RVSachin]

VHDL, unlike Verilog, is a strongly-typed language....meaning VHDL expects the width of Right hand side of the expression to be same as that of the left.

Since you are trying to divide a 8-bit vector and assigning it to 16-bit output, it will always error out. Try changing the widths of both sides to 8 or 16.

Also, synthesizable Division requires that the divisor should be a constant integer, which is power of 2.

You will be required to implement the division algorithm such as NON-RESTORING method if you are planning to divide a no. by a no. which is not a power of 2.