How to get a tristate condition

[aryajur]

Hello,
I am very new to VHDL and I have just started learning. I was curious to know how can one get a tristate condition to a gate in a VHDL code. Can it be done?

 

[VHDLguy]

Sure, here is a single bit output enable buffer. 'Z' is a high impedance state using std_logic

if enb = '1' then
out <= out_internal;
else
out <= 'Z';
end if;

If you want say an IO buffer with input and output:

if enb = '1' then
pad <= output;
else
pad <= 'Z';
end if;
input <= pad;

So input is always equal to whatever is on the pad, and if the enb is not set then something else is driving.