How to find signals whie doing post-layout simulation? 1

[AllEars]

Hi,
I am working with an FPGA design of hierarchic structure. The pre-layout simulation is successful but the post-layout simulaton is not as expected. I don't know how to find the problem, because all the signal names (except for the top-most port) in the post-layout simulation are generated by the synthesis/place/route tools, something like lmp_buffer_4_4_0_f. Is there a easy way to match (or map) my signal name in the original VHDL file with the signal name in back-annotated VHDL file generated by the synthesis/place/route tools?
Thanks for help.

 

[VHDLguy]

Usually there is a pragma that you set in your VHDL, or maybe a setting in your synthesis tool to say "preserve heirarchy". I think that is what you use to keep the signal names preserved also.

I forget exactly what it is, but in any event its usually different depending on your synthesis tool. So take a look through the help for "preserving heirarchy" and "preserving signal names".

--

http://www.lateralsands.com/

 

[AllEars]

Hi, VHDLguy:

Thanks for your reply. For my systhesis tool, LeonardoSpectrum for Atmel, Version: 2002c.37_OEM_Atmel, there is no progma related with the signal name usage. At least in the help I could not find one through search.

By the way, I found my VHDL code is not well designed from synthesis point of view. I'm going to modify the code and give another try.

 

[senjed]

Something usually done in such situations is, look for signals you think may have caused the problem, and extract them, i.e. assign them to ports, just to see whta happens to them.