How do I design a race timer in VHDL ?

[trickae]

The aim of this experiment is to design and construct a race timer, suitable for use in track events, where the times of place getters are displayed on seven segment LED displays. The circuit is to start counting on receipt of a pulse from a starting button, and to record the times of arrival of the place getters. You are asked to design and construct
two dierent circuits, the rst displaying the rst two place getters only, while the second and more involved circuit stores and displays the time for the rst three place getters. We will restrict the timing precision to two digits only { seconds and tens of seconds { although the extension to higher precision should be obvious.

Timer C:

should be able to register and display the times of the first 4 place getters in a race. A single pair of seven segment LED's should display one place getter's time (0-99). Timer C should have 4 inputs: a reset and input X as in Timer B, and switches S1 and S0 to select which of the 4 plagetter's time to display on the pair of 7 segment LED's.


- any advice on how to go about this? Last weeks lab had us do FSM, mealy models and 4bit counters.

Thanks in advance for any help

 

[trickae]

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity timer is
    port (
	clk_in: in STD_LOGIC;
    	reset: in STD_LOGIC;
        push_button: in STD_LOGIC;
        current_state: out STD_LOGIC_VECTOR (1 downto 0);
        digit0: out STD_LOGIC_VECTOR (3 downto 0);
        digit1: out STD_LOGIC_VECTOR (3 downto 0);
        digit2: out STD_LOGIC_VECTOR (3 downto 0);
        digit3: out STD_LOGIC_VECTOR (3 downto 0) 
    );
end timer;

architecture timer_arch of timer is

signal count_enable0: STD_LOGIC;	--enable signal for 1st counter
signal count_enable1: STD_LOGIC;	--enable signal for 2nd counter
signal count_out0: STD_LOGIC;		--countrol output of 1st counter
signal count_out1: STD_LOGIC;		--countrol output of 2nd counter
signal count_out2: STD_LOGIC;		--countrol output of 3rd counter
signal count_out3: STD_LOGIC;		--countrol output of 4th counter

signal next_state: STD_LOGIC_VECTOR (1 downto 0);	--next state variables
signal present_state: STD_LOGIC_VECTOR (1 downto 0);	--present state variable

signal clk_out: STD_LOGIC;				--divided clock output
signal clk_divider: STD_LOGIC_VECTOR(3 downto 0);	--clock divider counter

CONSTANT A: STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";		-- state A
CONSTANT B: STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";		-- state B
CONSTANT C: STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";		-- state C
CONSTANT D: STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";		-- state D


----------------------------------------
--BCD counter component - DO NOT MODIFY
----------------------------------------

component bcd_counter
	port (
        	reset: in STD_LOGIC;
	        clk: in STD_LOGIC;
	        count_enable: in STD_LOGIC;
	        carry_out: out STD_LOGIC;
	        digit_out: out STD_LOGIC_VECTOR (3 downto 0)
	    );
end component;

begin


	-------------------------
	--FSM flip flop process, 
	-------------------------
	process(push_button, reset) 
	begin

		--Reset the FSM to state A if the reset
		--signal is low.
		if reset = '0' then
			present_state <= A;
		
		--The FSM state changes on the rising edge of the push button.
		--The physical push button has been compensated for switch bouncing.	
		elsif push_button'EVENT and push_button = '1' then
		
			present_state <= next_state;
		end if;
	end process;

	----------------------------------------	
	--FSM next state logic process
	----------------------------------------
	process(present_state)
	begin
		case present_state is
			
			-----------------------------------
			--ENTER YOUR NEXT STATE LOGIC HERE	 
			--Design the controller as an FSM. 
			--Choose the type of FSM (Moore or Mealy) 
			--to suit the problem, but remember that 
			--Moore is always easier to design with reliably.
			-----------------------------------			
		
		end case;
	end process;

	---------------------------------------------------------------
	--Enter Your connecting logic for the FSM to counter interface.
	---------------------------------------------------------------

	        
        --clock divder process is used to lower 
		--the clock speed by using a counter.
        process(clk_in, reset)
        begin

		-------------------------------------
		--ENTER YOUR CLOCK DIVIDER LOGIC HERE
		--Decide what clock frequency you need in your design. 
		--Use the clock signal from the clock generator supplied 
		--in the timer design template file to obtain appropriate clock for your design.
		-------------------------------------					
        	
        end process;
        
	--Link clock divider output to the clock divider counter.
        clk_out <= clk_divider(3);
    
 
end timer_arch;

I'm given this template for timer A - I need to design a Finite state machine (mealy or a moore (moore's are easier)) to implement the above solution. Any help?