Hierarchical signal probing in VHDL

[maxnil]

Is there any way in VHDL to 'probe' a local signal that is located in a sub block at a lower level in the design hierarchy? In Verilog you can write:
assign kalle = top_block.sub_block_a.sub_block_b.signal_x if you whant to 'look' at 'signal_x' that is in 'sub_block_b'.

 

[VHDLguy]

seems to me like you can, but I forget how.

I know there is an attribute called 'simple name to return a signal name with no library declaration etc.

according to ashendon library.package_name.constant_name'simple_name
will return "constant_name"
but I am unsure if this only works for packages, or constants or what.

In any event it doesn't take into account the design heirarchy so it surely can't work for multiple instantiations.

there is also an attribute called 'path_name which returns the heirarchy path to a location. useful in reports so that you can tell what caused the error. These path's return with colon seperators, so you could try that.

try using the 'path in a report and then copy the result to see if you can access signals that way.

--

http://www.lateralsands.com/

 

[VHDLguy]

note that those attributes are not in VHDL 87

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http://www.lateralsands.com/