Hi guys, when I try to do a post

[edhunter2003]

Hi guys,

when I try to do a post-translate simulation of some code of mine, i get the following error

# WARNING[1]: zerorunlength_translate.vhd(3730): No default binding for component: "x_lut2". (No entity named "x_lut2" was found)[\code]

Any idea what the problem could be?

Also, when I synthesise the code, I get the following errors

[code]WARNING:Xst:737 - Found 1-bit latch for signal <rdy_int>.
WARNING:Xst:737 - Found 1-bit latch for signal <dr_int>.[\code]

They seem to be associated with the lines

[code]rdy_int <= '1' when rdy_sig = '1' 
	else '0' when rst = '1' or countBuf = countOut
	else rdy_int;
dr_int <= '1' when dr = '1' or rst = '1' 
	else '0' when countOut = countBuf
	else dr_int;[\code]

Any help would be appreciated.

Thanks
Ed

 

[edhunter2003]

Also, I am having a problem with the waveform viewer in ModelSim. When I try to add signals to the waveform viewer, some of them cause the ModelSim application to close down completely, with no error or warning. Others cause the following warnings

# ** Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use.
# File in use by: arm  Hostname: ELEC222  ProcessID: 704
#           Attempting to use alternate file "C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\wlftìáé2".
# ** Warning: (vsim-WLF-5001) Could not open log file vsim.wlf.  Using C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\wlftìáé2 instead.[\code]

Thanks
Ed

 

[edhunter2003]

I fixed the problem in my second posting. It was because I was accessing a project on a networked PC that was accessed by another user.

The first warning in my first post is also occurring in files that previously worked in a post-translate simulation.

 

[VHDLguy]

Usually no default binding warnings occur when you are simulating across multiple libraries.
The best way to get around the problem is to create a configuration and compile that.

However by port-translate I assume that you mean that you are trying to simulate synthesised vhdl. In which case a configuration is probably not feasible.

My next question would be: Does the compiled library in which x_lut2 occurs exist?

 

[VHDLguy]

As for the warnings about latchs... You created a latch!

rdy_int <= '1' when rdy_sig = '1'
else '0' when rst = '1' or countBuf = countOut
else rdy_int;


by refering to rdy_int, within combinatorial code, you have created a latch. In order for rdy_int be set to rdy_int (during certain conditions) you need to create a register with enable (or a latch).

You can do this, its legal. But there are a number of issues with using Latchs. Hence the warning message.

You can also create a latch unintentionally if your if/case statement does not catch all siuations. For example if you did not have the else statement, it would still be a latch since it doesn't know what to do when the other if statements are not true.

So to remove the latch problem, you would need to either:

rdy_int <= '1' when rdy_sig = '1'
else '0' when rst = '1' or countBuf = countOut
else '0';

or

rdy_int <= '1' when rdy_sig = '1'
else '0' when rst = '1' or countBuf = countOut
else some_other_signal;

or

rdy_int <= '1' when rdy_sig = '1'
else '0' when rst = '1' or countBuf = countOut
else some_other_signal when rdy_sig /= '1';

there are some examples. However sometimes you just can't do what you are trying to do and then you must clock the signal. or use a latch if you decide its ok.