Hey guys I am getting the error tha

[sheenjrg]

Hey guys I am getting the error that the design is too large to fit in the device(Xilinx webpack and I am using Spartan-II). In the Design details I see the number slices is 1211/1200 and I have like 124 slices of unrealated logic.
I would like to know if there is a way we can increase the size of the device without reducing the logic? Or any way to make the logic efficient and smaller?

 

[VHDLguy]

Well, short of buying another device and changing your board to accomodate it, your only option is to reduce your logic.

You may be able to buy a bigger device with the same footprint, so no board changes are needed apart from removing a device and adding another.

But since you are close it shouldn't be too difficult to reduce your logic.

There are a couple of things you could look for
1. Big sift registers/FIFOs that don't really need to be as big as you made them
2. Big combinatorial logic that could be rewritten to be more efficient. (ie big if-then-else statements).
3. reset conditions that you don't really need (eg reseting every stage of a shift register - a few clocks will do the same thing if the start of the shift is reset and no conditions hinder the propagation of the reset values).

There is a place to start.

--

http://www.lateralsands.com/

 

[sheenjrg]

Thanks dude I did it by reducing logic. Luckily I was not over by much so could resolve by removing some unnecessary logic.