Help with VHDL FIFO

[wheels21]

Hello everyone, I am trying to code a FIFO in VHDL, the language is fairly new to me, and so are FIFOs. I was wonder if there is anyone out there who could help me with the fundamentals or some helpful advise on the correct ways to do it. It would be greatly appreciated.

Wheels21

 

[RVSachin]

Hi,

For someone who is new to VHDL, I feel it will be difficult to straight away design a FIFO. You can probably start with designing basic digital elements using VHDL and later think about FIFO.

As far as designing FIFO is concerned, you can go for structural approach where the FIFO is designed as a combination of various components such as the READ and WRITE address generator, the RAM, the Contrl logic which includes coding the control flags such as FULL, EMPTY.

You can also refer to the link:

http://www.geocities.com/deepakgeorge2000/fifo.htm