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Help with selecting different test programs at compile time?

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gordwait

Technical User
Apr 21, 2005
3
US
I have a testbench setup, with a bus functional cpu model that can execute read/write cycles to a device under test.
I have various modes of operation, and I would like to create a number of different cpu "test programs" each to it's own VHDL file, and compile in the selected one at will.
I was hoping to create each test program as a procedure in a package, then link in the desired package when I run the simulation. The CPU model would then call the test procedure during simulations.

The trouble is that packaged procedures don't have access to signals in the calling CPU model.

So, I read you can declare signals in a package, to create a global variable. Seems like procedures declared in that same package can not access these global variables either??

Does anyone have a clean way to implement test subprograms in individual files?

If I make one CPU file with all the procedures declared in one architecture body, then it will simulate, but it means I have to duplicate all this every time I make a new test program. Imagine I have a regression suite with 50 test programs, and I need to make a fix to the cpu model? Now I have to update 50 copies of the CPU model...

Thoughts?
 
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