Hi
More info needed
what is there in the *.vhd, plus a few starting lines ?
what is your tool /& operating system / ?
is there anything reasonable written in the error message?
rgds
Here are the first few lines of code in bit_pack.vhd>
-- Bit package for Digital System Design Using VHDL
package BIT_PACK is
function add4 (reg1,reg2: bit_vector(3 downto 0);carry: bit)
return bit_vector;
function falling_edge(signal clock:bit)
return Boolean ;
Tool: Altera Max+plus II 9.21
OS: WinXP
Error: VHDL Design File "bit_pack" must contain entity of the same name
Thanks for the response!