I'm doing my project about data transmission, and i need to know the code on how to make a SERIAL RECEIVER, with a start bit and a stop bit and using a clk_16baud for sampling these bits.
Any help is greatly appreciated
Thanks
How about you make an attempt and we comment on what is wrong, what could be better etc.
Short of doing it for you, which I am not going to do, its kind of hard to describe.
To begin with lets create the device itself and ignore the testbench (if you actually even have to do that). So it doesn't really matter what the clock rate is, its just a signal name.
create a psuedo code of what you want to do. For a beginer that seems like a good way to start as you probably understand what I am talking about and its too hard (in ascii) to ask you to create the digital hardware and work backwards from there.
then create processes with wait statements to infer a clock
(ie. wait until clk_16baud'event and clk_16baud = '1').
In those processes create signals to do what you want with simple statements like if statements and case statements.
Post your psuedo code and resulting VHDL and I promise not to laugh if its really bad (can't speak for other though), We've all been there.
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