Help! Error: CSSIM0006!!!

[SamJamaica]

I'm asked to make a 32-bit ALU for a class assignment. It seems to be fine, but when i go to simulate, i get the following error:

Error: CSSIM0006: ALU32bit.vhd: (line 38): Bad array index (1) for dimension 1, allowed range is NULL
At ALU32bit.vhd: (line 38)

This assignment is due tonight at midnight (Eastern Time), so quick replies would be infintely appreciated!!

Below are the files for in my workspace:

alu1subb.vhd
-- behavioral model of the 1-bit ALU with subtraction enabled

library IEEE;
use IEEE.std_logic_1164.all;

entity alu1sub is
port(a,b,CarryIn : in std_ulogic;
Operation : in std_ulogic_vector (3 downto 0);
Result, CarryOut : out std_ulogic);
end alu1sub;

architecture behavioral of alu1sub is

signal a_line, b_line : std_ulogic;
constant gate_delay: Time:=5 ns;

begin

with Operation(3) select
a_line <= (not a) when '1', a when others;

with Operation(2) select
b_line <= (not b) when '1', b when others;

with Operation(1 downto 0) select
Result <= (a_line and b_line) after gate_delay when "00",
(a_line or b_line) after gate_delay when "01",
(a_line xor b_line xor CarryIn) after gate_delay when "10",
'X' after gate_delay when others;
CarryOut <= ((a_line and b_line) or (a_line and CarryIn) or (b_line and CarryIn)) after gate_delay;
end behavioral;

alu1ofsubb.vhd
-- behavioral model of the 1-bit ALU with overflow detection and subtraction

library IEEE;
use IEEE.std_logic_1164.all;

entity alu1ofsub is
port(a,b,CarryIn : in std_ulogic;
Operation : in std_ulogic_vector (3 downto 0);
Result,OverFlow : out std_ulogic);
end alu1ofsub;

architecture behavioral of alu1ofsub is
constant gate_delay: Time:=5 ns;

signal a_line, b_line : std_ulogic;

begin
with Operation(3) select
a_line <= (not a) when '1', a when others;

with Operation(2) select
b_line <= (not b) when '1', a when others;

with Operation(1 downto 0) select
Result <= (a_line and b_line) after gate_delay when "00",
(a_line or b_line) after gate_delay when "01",
(a_line xor b_line xor CarryIn) after gate_delay when "10",
'X' after gate_delay when others;
Overflow <= ((a_line and b_line) or (a_line and CarryIn) or (b_line and CarryIn)) after gate_delay;
end behavioral;

ALU32bit.vhd
--32 bit ALU, coded by N4T3 D0GG

library IEEE;
use IEEE.std_logic_1164.all;

entity ALU32 is
port(Ain : in std_ulogic_vector(32 downto 1);
Bin : in std_ulogic_vector(32 downto 1);
Operation : in std_ulogic_vector(3 downto 0);
Result : out std_ulogic_vector(32 downto 1);
Overflow : out std_ulogic
);
end entity ALU32;

architecture generate_ALU32 of ALU32 is

signal Carry_Line : std_ulogic_vector(31 to 1);

component alu1sub
port(a,b,CarryIn : in std_ulogic;
Operation : in std_ulogic_vector (3 downto 0);
Result, CarryOut : out std_ulogic);
end component;

component alu1ofsub
port(a,b,CarryIn : in std_ulogic;
Operation : in std_ulogic_vector (3 downto 0);
Result, OverFlow : out std_ulogic);
end component;

begin

ALU32GEN: for i in 1 to 32 generate
begin

LSB: if i = 1 generate
begin
ALU: component alu1sub
port map(Ain(i), Bin(i), Operation(2), Operation, Result(i), Carry_Line(i));
end generate LSB;

OB: if ((i > 1) and (i < 32)) generate
begin
ALU: component alu1sub
port map(Ain(i), Bin(i), Carry_Line(i-1), Operation, Result(i), Carry_Line(i));
end generate OB;

MSB: if i = 32 generate
begin
ALU: component alu1ofsub
port map(Ain(i), Bin(i), Carry_Line(i-1), Operation, Result(i), Overflow);
end generate MSB;

end generate ALU32GEN;

end generate_ALU32;

ALU32bit_TEST.vhd
entity ALU32bit_TESTer is
end entity;

architecture behavioral of ALU32bit_TESTer is

component ALU32 is
port(Ain : in std_ulogic_vector(32 downto 1);
Bin : in std_ulogic_vector(32 downto 1);
Operation : in std_ulogic_vector(3 downto 0);
Result : out std_ulogic_vector(32 downto 1);
Overflow : out std_ulogic
);
end component;

signal A_in, B_in, Result_out : std_ulogic_vector(32 downto 1);

signal Op_in : std_ulogic_vector(3 downto 0);

signal OvFl : std_ulogic;

begin
TopLevelToBeTested : ALU32
port map(Ain => A_in,
Bin => B_in,
Operation => Op_in,
Result => Result_out,
Overflow => OvFl
);

A_in <= "00000000000000000000000000000001" after 0 ns;
B_in <= "00000000000000000000000000000001" after 0 ns;
Op_in <= "0010" after 2 ns;

end behavioral;