help!!! binary to bcd converter

[yein]

I am successful synthesize the code but the delay is quite large...It's undesirable...
IS there any suggestion to revise the code?
The cct diagram and also the code with be attached here..
Thank for helping....


LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
USE ieee.STD_LOGIC_ARITH.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
use work.project.all;

ENTITY BinaryToBCD IS
port( D : in std_logic_vector(15 downto 0);
Q : out std_logic_vector(15 downto 0));
END BinaryToBCD;

ARCHITECTURE behavioral OF BinaryToBCD IS
signal sigA, sig1A: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigB, sig1B: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigC, sig1C: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigD, sig1D: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigE, sig1E: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigF, sig1F: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigG, sig1G: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigH, sig1H: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigI, sig1I: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigJ, sig1J: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigK, sig1K: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigL, sig1L: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigM, sig1M: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigN, sig1N: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigO, sig1O: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigP, sig1P: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigQ, sig1Q: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigR, sig1R: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigS, sig1S: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigT, sig1T: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigU, sig1U: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigV, sig1V: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigW, sig1W: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigX, sig1X: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigY, sig1Y: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal sigZ: STD_LOGIC_VECTOR(3 DOWNTO 0);

Begin
Process(D)
BEGIN
sigZ <= D(14 DOWNTO 11);
sigA <= ADD3_Module(sigZ);
sig1A <= sigA (2 DOWNTO 0) & D(10);
sigB <= ADD3_Module(sig1A);
sig1B <= sigB (2 DOWNTO 0) & D(9);
sigC <= ADD3_Module(sig1B);
sigD <= D(15) & sigA(3) & sigB(3) & sigC(3);
sigE <= ADD3_Module(sigD);
sig1C <= sigC (2 DOWNTO 0) & D(8);
sigF <=ADD3_Module(sig1C);
sig1E <= sigE(2 DOWNTO 0) & sigF(3);
sigG <=ADD3_Module(sig1E);
sig1F <= sigF(2 DOWNTO 0) & D(7);
sigH <=ADD3_Module(sig1F);
sig1G <= sigG(2 DOWNTO 0) & sigH(3);
sigI <=ADD3_Module(sig1G);
sig1H <= sigH(2 DOWNTO 0) & D(6);
sigJ <=ADD3_Module(sig1H);
sig1I <= sigI(2 DOWNTO 0) & sigJ(3);
sigK <=ADD3_Module(sig1I);
sig1J <= sigJ(2 DOWNTO 0) & D(5);
sigL <=ADD3_Module(sig1J);
sigM <= sigE(3) & sigG(3) & sigI(3) & sigK(3);
sigN <=ADD3_Module(sigM);
sig1K <= sigK(2 DOWNTO 0) & sigL(3);
sigO <=ADD3_Module(sig1K);
sig1L <= sigL(2 DOWNTO 0) & D(4);
sigP <=ADD3_Module(sig1L);
sig1N <= sigN(2 DOWNTO 0) & sigO(3);
sigQ <=ADD3_Module(sig1N);
sig1O <= sigO(2 DOWNTO 0) & sigP(3);
sigR <=ADD3_Module(sig1O);
sig1P <= sigP(2 DOWNTO 0) & D(3);
sigS <=ADD3_Module(sig1P);
sig1Q <= sigQ(2 DOWNTO 0) & sigR(3);
sigT <=ADD3_Module(sig1Q);
sig1R <= sigR(2 DOWNTO 0) & sigS(3);
sigU <=ADD3_Module(sig1R);
sig1S <= sigS(2 DOWNTO 0) & D(2);
sigV <=ADD3_Module(sig1S);
sig1T <= sigT(2 DOWNTO 0) & sigU(3);
sigW <=ADD3_Module(sig1T);
sig1U <= sigU(2 DOWNTO 0) & sigV(3);
sigX <=ADD3_Module(sig1U);
sig1V <= sigV(2 DOWNTO 0) & D(1);
sigY <=ADD3_Module(sig1V);
Q <= sigN(3) & sigQ(3) & sigT(3) & sigW & sigX & sigY & D(0);
end process;
end behavioral;

Sorry i dont know how to upload the cct...
the concepts are similar with this website and i have changed the circuit into 16 bits

http://www.engr.udayton.edu/faculty/jloomis/ece314/notes/devices/binary_to_BCD/bin_to_BCD.html