library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sort is
port(reset,clk:in std_logic;
sort_array :in std_logic_vector(3 downto 0);
data_out
ut std_logic_vector(3 downto 0));
architecture sort_a of sort is
type sort_array is array (0 to 4)of std_logic_vector(3 downto 0);
constant sample : sort_array :=(0000,0010,0100,0110,1000);
variable i : integer range 0 to 4 ;
process(clk)
begin
if rising_edge(clk)then
if reset="1";
data_out<=sample(i);
else
data_out<=(0000,1000,0010,0100,0110);
end if ;
end if;
end process;
end sort_a;
this is the error of this code , i want solution
near "process": expecting END
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sort is
port(reset,clk:in std_logic;
sort_array :in std_logic_vector(3 downto 0);
data_out
ut std_logic_vector(3 downto 0));architecture sort_a of sort is
type sort_array is array (0 to 4)of std_logic_vector(3 downto 0);
constant sample : sort_array :=(0000,0010,0100,0110,1000);
variable i : integer range 0 to 4 ;
process(clk)
begin
if rising_edge(clk)then
if reset="1";
data_out<=sample(i);
else
data_out<=(0000,1000,0010,0100,0110);
end if ;
end if;
end process;
end sort_a;
this is the error of this code , i want solution
near "process": expecting END
