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Generic in VHDL , Help me please

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melzayed

Technical User
Apr 22, 2003
2
CA
I would like to design a component using generic. This component calls another component that is also using generic.

example:

U1: n_bit_adder generic map (width => 8) port map (a => word_A, b => word_b, c => carry_in, y => addition_result);

In the previous example, the call for the component adder will bew used in a nother component called "Subtractor" that will also use generic width.

I compile my code, the compiler generates an error saying that ther are too many generics. I can easily turn around this problem by designing different components with different integers for each width. But I'm sure there is a way to it 100% generic.

Any clues ??? really appreciate your help!
 
Hi,

Is it possible to build a simple test case and share with us.
 
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