Generate a 2 µs high level logic with a 10 MHz clock ?

[Olivier2412]

Hi !

I am using an ACTEL ProAsic Plus Starter Kit with an APA300 for the FPGA.

I would like to optimize the VHDL and I am asking the following question : To command an ADC, I need to generate a SAMPLE signal (high logic during at least 2 µs) but my whole design runs at 10 MHz.

To generate it, I am using a 4 bit counters but I am wondering if a better solution exists ? (like using a Flip-flop cascades to slow down the input clock)

What can you advise ?

Thanks a lot for your answer !