GENERAL VHDL Question

[Warrioruw]

Hi all,

I have some difficulities in programing VHDL. It is often the case that simulation timing diagram does not match what I expected, or sometimes I don't know why a certain value appear at another clock cycle. In plain text, I don't understand how VHDL code really works.

How do I think in HARDWARE? I know delta cycle and RTL simulation algorithm, but I don't have the feel of how it helps to interpret "Hardware Run in Parallel", because it's kind of hard to do the timing analysis every time.


Help and comments are appreciated!

Plz!

 

[jeandelfrigo]

Warrioruw,

I'll give it a shot trying to explain "parallelism".

I don't know if you are somewhat familiar with how software works, mainly how a processor runs software (example C code).

Every processor start running the code top down as one big sequence. The basic ways of preventing this is using loops or branch statements.

So if you have a software program you want to perform several times your main routine if we stick to C language will be a loop somethimes even while(1).

But the basic thing is that a processor can only perform one action per clockcycle (in practice most processor require even a couple of clock cycles to perform a C statement) but if we say it in assembly a processor can perform most instructions one instruction per cycle. Let's forget about enhancements such as prefetch and other fancy stuff.

So a processor can perform either a branch if equal or a sum or a shift but it cannot perform these actions all in one cycle.

Now lets switch to hardware or VHDL (same is true for verilog by the way).

In VHDL code there are different processes and they all operate simulaneously. Or better yet they can operate at the same time. This is why for simulation different delta cycles are required because the transition caused by one process to a signal can influence another processes that uses this signal. And the sequential processor simulation this code cannot do this at the same time, therefor one instance in time is split up in several delta cycles.

Lets take the following example :

pA : process(clk,rst)
begin
if (rst = '1')then
Q <= '0';
elsif(clk'event and clk = '1')then
Q <= 'D'; -- D is input to the entity
end if;
end process pA;

pB : process(clk,rst)
begin
if (rst = '1')then
T <= '0';
elsif(clk'event and clk = '1')then
if (D = '1')then
T <= '0';
else
T <= '1';
end if;
end if;
end process pB;

pC : process(D,Q,F)
begin
if(D = '0')then
if ( Q = '1' and F = '0')then
G <= '1';
else
G <= '0';
end if;
else
G <= D;
end if;
end process pC;

Do not pay any attention to the functionality of the code above. What we have is 3 processes, 2 are synchronous processes with an asynchronous reset and one is a full combinatorical process.

First of all the code of a VHDL process is "executed" whenever ther is a event (= change) on one of its signals in the sensitivity list, this is the list of signals after process between ().

So take the first process it will only be entered if there is a change on either rst or clk. Due to the hierarchy of the language if there in this case the reset will have more say then the clk. So every clock edge (rising) Q will take the value of D and at the same moment (edge) T will get a value depending on the value of D

So lets say that rst is '0' then every clock edge processes A and B will become active. So every clock edge Q and T get a new value ( note that I say new and not changing value)

Every rising clock edge Q will get the value of D and every same clock edge T will become the invers of D. At the same moment.

Now take process C, this process will be entered every time D and F change and the code in the process will be evaluated and G will get the resulting value described. Now in hardware Q will take the value of D a little nano moment after the clock edge (the clock to output delay). Because Q changes process C will be entered again.

This stuff keeps going on and on.

So remember that all processes can be active at the same time because they in fact describe parallel logic.

Lets say you describe two adders each in there own process.
Well the result will be two adders in real. This means if you have two seperate adders you can perform two additions at the same time if you want to.
If we go back to the processor it normally only has one ALU.
So if you want to perform two additions you will need to do them sequentially because you have only one adder and thus can perform only one addition at a time.

So this is why if you were to describe an ethernet core in one processes (normally it won't work) and you have an USB core in another process (also not the case in real) you can do both ethernet transactions and usb transactions at the same time because you have all the resources (flip flops, RAMS, logic) available to perform them both at the same time.

I do not know, but I hope this has clarified it somewhat for you. But I know also that is is a little difficult to understand and even more difficult to explain. In my expierence you need to try to understand it and once you have made the click it will all become very clear. But it can take a while for the click to come, especially for people with a pure software history or background.

What might help is starting with a simple VHDL file with two or three processes, where one process's output is used as an input in another process.
Then you simulate this file and normally it will become clear that the different processes can be working at the same time.

regards

jeandelfrigo