first ever code

[minigecko]

I'm an absolute beginner, and this is my first ever code.

Can someone tell me whats wrong? I have an "unexpected wait"
Below is my entire code, which I am compiling in "symphony", "Quartus II" is also on my machine.

From my C++ knowlage I reckon its an include thing that im missing, like the "library ieee;" line, i think i need another similar line, but i really have no idea, Please help.



library ieee;

entity clockt is
port( clk: out bit);
end clockt;

architecture tick of clockt is

begin
clk <= '1';
wait for 10ns;
clk <= '0';
wait for 10ns;
end tick;

 

[jeandelfrigo]

minigecko,

First of all do not use any C/C++ thoughts when you write VHDL.
C/C++ is for software and VHDL is for Hardware.

your code should be like this :

begin

process
begin
clk <= '1';
wait for 10ns;
clk <= '0';
wait for 10ns;
end process;

end tick;

Some more information :

This code will never synthesize.

Try to use the std_logic library and try to do everything at the pace of a clock (synchronous). Of cource your code is good to generate a clock in a testbench.
Think of a CPU, it's a (complex) peace of hardware that processes at the pace of a processor clock.

Also

What you write between begin and end of the architecture is performed in parallel.

Every Statement and/or process is performed simultaniously or also known as concurrent.

for example :

begin

X <= A xor B;

Z <= '1' when R = '1' else '0';

process(clk)
begin
if( clk'event and clk = '1')then
E <= not R;
end if;
end process;

end XXX;

The two lines and the process run in parallel at the same time.

I hope this is usefull info for you.

regards
Jeandelfrigo

 

[minigecko]

I am starting to understand the syntax now, thanks for the reply, it was a huge help. I now understand most of your post.

I was compiling using VHDL Simili 3.0, but now I'm trying to use Quartus II 5.0, which I think is more functional, with the picture bit I hope will prove useful.

When I compile the code from your post (which I am using as a testbench now) i get an error.
-----------
entity clock1 is
port( clk: out bit);
end clock1;

architecture struct of clock1 is
begin
process
begin
clk <= '1';
wait for 10 ns; --line 10 with the error
clk <= '0';
wait for 10 ns;
end process;
end struct;
--------------
Error: VHDL Wait Statement error at clock1.vhd(10): Wait Statement must contain condition clause with UNTIL keyword
...more errors...
-------------

The code compiled in simili, and agrees with all documentation i can find. Can anyone tell me what I'm doing wrong?

Thanks in advance!

 

[jeandelfrigo]

minigecko,

The code I posted for generating a clock signal is only usable in testbenches, this means it will not synthesize.

Also the entity of a testbench is allways empty.
You should see a testbench as a simulation of the real world, the environment of your FPGA or PLD. That is why it has no ports, where would it interface to?

In a testbench you write 'software' you describe how input ports of your design will behave. That is why in a testbench you can write things like wait for 10 ns, inside a real FPGA or PLD how would the FPGA now when the 10 ns are passed?

A real FPGA nows this only because there is a new rising (or falling) edge on a real clock signal of 50MHz (period 20 ns).

so a testbench should look like this.

lets assume you design is the entity design
It has a clock input and one other input and one output.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity design_tb
-- empty
end design_tb

arhitecture behavior of design_tb is

component design
port (
clk : in std_logic;
input : in std_logic;
output : out std_logic
)

signal clk : std_logic;
signal input : std_logic;
signal output : std_logic;

--component instantiation
-- this is where you map the internally generated signals
-- in your testbench to the ports of your design

i_design : design
port map(
clk => clk,
input => input,
output => output
);

-- now here are the generated inputs for your design

-- a 50 MHz clock (period is 20 ns)
procClock : process
begin
clk <= '0';
loop
wait for 10 ns;
Clk <= not Clk;
wait for 10 ns;
end loop;
end process procClock;

-- process that describes how input will behave in time
-- because a testbench will never be synthesized you can
-- easily tell the simulator to wait for xxx ns or yyy us
procGenInput : process
begin
input <= '0';
wait for 200 ns;
input <= '1';
wait for 20 ns;
input <= '0';
wait for 150 ns;
input <= '1';
wait for 40 ns;
input <= '0';
wait;
end process procGenInput;

end behavior;

So basically a testbench is allways an empty entity and in the architecture you generate the inputs for the design you want to test and map these genrated signals to the ports of your design.

I hope this is clear for you?
If not let me know I'll try to explain it some more.

Just for info?
How are you learning VHDL?
From a book? In a course?

For information I am not familiar with simili, I use modelsim to simulate my designs. I do have expierence with Quartus, but mostly for synthesis.

Regards
jeandelfrigo

 

[minigecko]

I'm only using Quartus now, as it has a the simulation tools that i used simili for.

Your explination is great, thanks for your time, it all seems so much simpler now (but not simple)! Any newbies, read this^^ post and follow it through, it is really worth it.

I'm learning from a CD(esperan) and i have a book and the web for reference.

Thanks jeandelfrigo, Much appreciated!