FIR filter error when Synthesized

[Sally000]

Hi,
I wrote a VHDL code for a 4 tap fir filter. I am not getting errors when I compile and simulate using altium designer. but when I put in Xilinx ISE 9.2i I'm getting an error saying

" Line 34. Choices for an array aggregate (Attribute name) must be locally static unless there is only one choice. (LRM 7.3.2.2)
which I don't understand. Can someone please help!! I need to solve this ASAP
this is the whole code...

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity FIR_Test is
GENERIC (n:INTEGER:=4; m: INTEGER :=4);
Port (x:in SIGNED(m-1 downto 0);
clk,rst:in std_logic;
yut SIGNED(2*m-1 downto 0));
end FIR_Test;
ARCHITECTURE RT1 of FIR_Test is
TYPE registers IS ARRAY (n-2 DOWNTO 0) OF SIGNED(m-1 DOWNTO 0);
TYPE coefficients IS ARRAY (n-1 DOWNTO 0) OF SIGNED (m-1 DOWNTO 0);
SIGNAL reg : registers;
CONSTANT coef: coefficients :=("0001" , "0010" , "0011" , "0100");
BEGIN
PROCESS(clk,rst)
VARIABLE acc, prod:
SIGNED(2*M-1 DOWNTO 0) := (OTHERS=> '0');
VARIABLE sign : STD_LOGIC;
BEGIN
IF (rst='1') THEN
FOR i IN n-2 DOWNTO 0 LOOP
FOR j IN m-1 DOWNTO 0 LOOP
reg(i)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (clk'EVENT AND clk = '1') THEN
acc := coef(0)*x;
FOR i IN 1 TO n-1 LOOP
sign := acc(2*m-1);
prod := coef(i) * reg(n-1-i);
acc := acc + prod;
IF (sign=prod(prod'left)) AND (acc(acc'left) /= sign)THEN
acc := (acc'LEFT => sign, OTHERS => NOT sign);
END IF;
END LOOP;
reg<= x & reg(n-2 DOWNTO 1);
END IF;
y<= acc;
END PROCESS;
END rt1;

Please please help ;(