file I/O simulation

[xpp2000]

I have the following code used for file I/O simulation under XilinX ModelSim env. When I try to output std_logic_vector in integer format for easy read.
It generate the following error(output binary is OK)
How to modify this code so that I can output signal in decimal or hex format?
Thank you!!

# ERROR: chanoneTB.vhd(109): Illegal type conversion
# ERROR: chanoneTB.vhd(110): Illegal type conversion
# ERROR: chanoneTB.vhd(111): Illegal type conversion
# ERROR: chanoneTB.vhd(128): VHDL Compiler exiting
# ERROR: C:/Modeltech_xe/win32xoem/vcom failed.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
.....
rw_vector: process --(clk_60m)
file INFILE : text is in "vector.txt";
file OUTFILE : text is out "out_vector.txt";
variable RD_BUFFER : line;
variable WR_BUFFER : line;
variable IN_VECTOR : std_logic_vector(16 downto 0);
variable sig_IN, sig_A, sig_B : integer;

begin
wait until (clk_60m = '1' and clk_60m'event);
while(not endfile(INFILE)) loop
readline (INFILE, RD_BUFFER);
read (RD_BUFFER, IN_VECTOR);
rdata <= IN_VECTOR(16 downto 5);
rtime <= IN_VECTOR(4);
cm <= IN_VECTOR(3 downto 1);
cd <= IN_VECTOR(0);
sig_IN := integer(rdata); -- line 109
sig_A := integer(CRDA); --line110
sig_B := integer(CRDB); -- line 111

--write (WR_BUFFER, rdata);
write (WR_BUFFER, sig_IN);
write (WR_BUFFER, string'(&quot; &quot);
--write (WR_BUFFER, CRDA);
write (WR_BUFFER, sig_A);
write (WR_BUFFER, string'(&quot; &quot);
--write (WR_BUFFER, CRDB);
write (WR_BUFFER, sig_B);
writeline(OUTFILE,WR_BUFFER);
wait until (clk_60m = '1' and clk_60m'event);
end loop;
assert FALSE report &quot;TEST Finished!&quot; severity Failure;
wait;
end process;

 

[VHDLguy]

One way to do it would be the to_integer function in numeric_std library.

It requires an unsigned so you could typecast the std_logic_vector to unsigned.

sig_IN := to_integer(unsigned(rdata));

There may be better ways to do it - but off the top of my head this should work.