Fiji007 during Mids only on one side

[jimc35]

I have been getting Fiji007 errors during mids under LD 30 but only when CPU 0 is the active core. No issue with CPU 1. I've done a 360 test and stat ring in LD 39 but no issues. Any ideas?

TIM7243 01:00 21/6/2017 CPU 0

DROL000 DAILY ROUTINE BEGIN
NWS LD30 BEGIN 01:00 21/6/2017

XMI000 36 : PLL UNLOCK EVENT

XMI000 4 : PLL UNLOCK EVENT

XMI000 8 : PLL UNLOCK EVENT

ERR080 36 0 4 4 117

FIJI007
NEW STATE RING 0: NONE
RING 1: FULL

FIJI010 1 0 ALARM 00 - RECVS_FROM 00000003

FIJI007
NEW STATE RING 0: HALF
RING 1: HALF

FIJI010 1 0 ALARM 00 - RECVS_FROM 00000002

FIJI007
NEW STATE RING 0: NONE
RING 1: FULL

FIJI010 1 0 ALARM 00 - RECVS_FROM 00000003

FIJI007
NEW STATE RING 0: HALF
RING 1: HALF

FIJI010 1 0 ALARM 00 - RECVS_FROM 00000002

FIJI007
NEW STATE RING 0: NONE
RING 1: FULL

FIJI010 1 0 ALARM 00 - RECVS_FROM 00000003

FIJI007
NEW STATE RING 0: HALF
RING 1: HALF

FIJI010 1 0 ALARM 00 - RECVS_FROM 00000002

FIJI007
NEW STATE RING 0: NONE
RING 1: FULL

XMI000 36 : PLL UNLOCK EVENT

FIJI010 1 0 ALARM 00 - RECVS_FROM 00000000

FIJI011 1 0 ALARM ON 01 - LOP

FIJI055

XMI000 52 : PLL lock lost

XMI000 40 : PLL lock lost

NWS501 4 0 0 : -5

NWS501 4 0 14 : -11

NWS501 8 0 0 : -9

NWS401 8 0 15 : -0 -13

NWS401 8 1 0 : -9 -12

NWS501 8 1 4 : -7

XMI000 52 : PLL locked

XMI000 40 : PLL locked

FIJI005 RING 0

FIJI010 1 0 ALARM 00 - RECVS_FROM 00000003

FIJI005 RING 0

FIJI011 1 0 ALARM OFF 01 - LOP

FIJI007
NEW STATE RING 0: HALF
RING 1: HALF

NWS501 20 0 8 : -6

NWS401 20 0 9 : -1 -2 -7

NWS501 20 0 11 : -10

NWS501 52 0 1 : -14

NWS501 52 0 2 : -14

NWS501 52 0 4 : -1

NWS501 52 0 7 : -10

DROL001 DAILY ROUTINE END
NWS LD30 END 01:02 21/6/2017 []

 

[KCFLHRC]

Could be a clock controller issue. If you have the new Global Clock Controllers you can do a force download on them

 

[KCFLHRC]

CS1000: FIJI Rings Operates Incorrectly
Rate Content Rate this Page

Doc ID: SOLN149022
Version: 6.0
Status: Published
Published date: 23 Sep 2011
Updated: 24 Feb 2016
Author:
Somesh Nistala

Details

CS1000

3.0 - 7.65
Problem Clarification

FIJI055 [Clock switch] and FIJI018 0 0 ALARM OFF 33 - PLL_LOL_78M FIJI010 1 0 ALARM 00 - RECVS_FROM 00000002 FIJI010 1 0 ALARM 00 - RECVS_FROM 00000003.'

Intermittently FIJI Rings operates incorrectly. Ring 0 and Ring1 status is changing from Half /half to None/Full NEW STATE RING 0: HALF RING 1: HALF FIJI007 NEW STATE RING 0: NONE RING 1: FULL.
Cause

FIJI055 [Clock switch] and FIJI018 0 0 ALARM OFF 33 - PLL_LOL_78M messages SONET interface and 32MHz clock is used for the backplane interface.
Two things can cause PLL unlock:

One is that reference clock frequency wanders out of the lock range
The other thing is a significant phase shift of the reference signal.

Since every FIJI in non-group 0 tries to track the clock from the next upstream FIJI, a clock disturbance on one FIJI will see its effect on every FIJI downstream. In group 0, this disturbance will be stopped because the FIJI in group 0 only tracks to the clock controller.

This alarm is usually the result of an unstable clock oscillation on the ring, or a bad FIJI card up-stream. FIJI010 1 0 ALARM 00 - RECVS_FROM 00000002 FIJI010 1 0 ALARM 00 - RECVS_FROM 00000003 Which is usually caused by a clocking disturbance this could be referring a bad cabling issue as wells a bad CC.
Solution

Given following action plan to fix the issue:

Swap clocks numerous times.
If issue persists, disable and reseat all FIJI cards in Ring 0. Enable cards. Try to duplicate issue by swapping clocks numerous times.
If issue persists, replace NTRC49 clock card to clock card cable. Try to duplicate issue by swapping clocks numerous times.
If issue persists, replace clock NTRC46 clock to FIJI card cable. Try to duplicate issue by swapping clocks numerous times.
After implementing step 1 , the FIJI Rings should be stable, no messages related to FIJI should be present on the system.