unlimitedxp
IS-IT--Management
Hi all,
I am designing an FFT/IFFT processor in VHDL. I am done with my RTL but while back annotating it i am facing a problem which says thyat "Illegal Refernce to non varaible 'count'".Actually count is a control master which takes care of all the blocks functionality. Unfortunately what i am doing is that my code is in VHDL but during synthesis i am writing the .db file in verilog as i dont have the VHDL simulations models.
Will it work ???? Is this error because of incompatability or something else???/
Please help
I am designing an FFT/IFFT processor in VHDL. I am done with my RTL but while back annotating it i am facing a problem which says thyat "Illegal Refernce to non varaible 'count'".Actually count is a control master which takes care of all the blocks functionality. Unfortunately what i am doing is that my code is in VHDL but during synthesis i am writing the .db file in verilog as i dont have the VHDL simulations models.
Will it work ???? Is this error because of incompatability or something else???/
Please help