ERROR: XST failed - Process "Synthesize" did not complete.

[malalation]

Hello everybody,
I'm trying to do my own version of the PPI as a college project using VHDL, I made 4 processes, there are no syntax errors but there is the following error:
ERROR: XST failed
Process "Synthesize" did not complete.
I checked the parameter list of the processes, but I found out that everything is ok.

pllllllllz help me to find where I've gone wrong :S


here is the code:



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity myPPI is
port(CS,RD,WR,Reset: in bit;
A: in std_logic_vector(1 downto 0);
PA,PB,Data: inout std_logic_vector(7 downto 0);
PCU,PCL: inout std_logic_vector(3 downto 0)
);
end myPPI;

architecture myPPI_arch of myPPI is
signal CR: std_logic_vector(7 downto 0); --for the Control Register
signal PAint,PBint: std_logic_vector(7 downto 0);
signal PCUint,PCLint: std_logic_vector(3 downto 0);
begin

process(WR,CS,CR,A) --for righting values into the registers
begin
if(CS = '0')then
if(WR = '0')then --The Writing Operation
if(A="00" and CR(4) = '0')then
PAint <= Data; --Storing in PortA
elsif(A="01" and CR(1) = '0')then
PBint <= Data; --Storing in PortB
elsif(A="10") then
if(CR(0) = '0')then
PCLint <= Data(3 downto 0); --Storing in PortC Lower
end if;
if(CR(3) = '0') then
PCUint <= Data(7 downto 4); --Storing in PortC Upper
end if;
elsif(A="11")then
CR <= Data; --Storing in the Control Register
end if;
end if;
end if;
end process;

process(RD,CS,CR,A) --for reading the values of the registers
begin
if(CS = '0')then
if(RD = '0')then
if(A="00" and CR(4) = '1')then
Data <= PAint; --Reading from PortA
elsif(A="01" and CR(1) = '1')then
Data <= PBint; --Reading from PortB
elsif(A="10") then
if(CR(0) = '1')then
Data(3 downto 0)<= PCLint; --Reading from PortC Lower
end if;
if(CR(3) = '1')then
Data(7 downto 4)<= PCUint; --Reading from PortC Upper
end if;
end if;
end if;
end if;
end process;

process(CR,CS) --for outputting the out ports
begin
if(CS = '0')then
if(CR(4) = '0')then
PA <= PAint;
end if;
if(CR(1) = '0')then
PB <= PBint;
end if;
if(CR(0) = '0')then
PCL <= PCLint;
end if;
if(CR(3) = '0')then
PCU <= PCUint;
end if;
end if;
end process;

process(CR,CS) --for inputting the in ports
begin
if (CS = '0')then
if(CR(4) = '1')then
PAint <= PA;
end if;
if(CR(1) = '1')then
PBint <= PB;
end if;
if(CR(0) = '1')then
PCLint <= PCL;
end if;
if(CR(3) = '1')then
PCUint <= PCU;
end if;
end if;
end process;

process(Reset,CS) --for Reset
begin
if (CS = '0')then
if(Reset = '1')then
CR <= "00000000";
end if;
end if;
end process;


end myPPI_arch;

 

[jeandelfrigo]

My dear friend,

One do not use the word register in your comment.
You do not have a single register in your code.

register is like this

p_reg: process(clk)
begin
if(clk'event and clk = '1')then
Q <= D;
end if;
end process p_reg;

registers only have the clock in the sensitivity list.
You can add the reset if you want to do an asyncrhonous reset, but most FPGA architecture result in fewer logic with synchronous resets.

Of course if your compiling for CPLD then I can understand your code a little better.

What you have written is a bunch of latches.
Your synthesizer report should contain several latch errors.

I do not see any conflicts for the rest in the code, although I haven't read it in detail.
But then you would get multiple driver warnings.

A few tips, your using ISE check out the code templates, they might be useful.

Also there are probably some more message above the XST failed, these are more useful to find out what is causing the failure. You might wanna look at them or even post them on this thread then I (or others) can help you out some more.

regards

jeandelfrigo