ERROR Use "set -loop_iteration_limit XX"

[astrophobic]

hello

i made the following programm for a seriel parity generator.
the problem is if i try to synthesize it i get the following error:

ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more.

the program:

entity paritaet_seriel is
port( D_IN, CLK: std_logic bit;
STARTBIT, STOPBIT: in boolean;
D_OUT: std_logic bit
);
end paritaet_seriel;

architecture Behavioral of paritaet_seriel is
begin
P1: process
variable PAR: boolean;
begin
wait until(CLK'event and CLK = '1');
if STARTBIT then
PAR:= false;
while not STOPBIT loop
if CLK = '1' and CLK'event then D_OUT <= D_IN;
if D_IN = '1' then PAR:= not PAR;
end if;
end if;
end loop;
end if;
if PAR then
D_OUT <= '1';
else
D_OUT <= '0';
end if;
end process P1;
end Behavioral;

i use the xilinx ise WebPack.

br tobias

 

[berett]

Hi
The soft just want you to enable more iterations of the loop because the code needs more than 64 etc.

But the real problem seems the double clk'event statement in the same process which probably makes the synthesizer sick. BTW I can't imagine the appropriate hardware to do the code ...

Why not to use the latched flip-flop which triggers when the bit is '1', stops counting when the stopbit comes etc ...

eg:

process(clk, reset)
begin
if reset = '0' then
parity <= '0';
elsif CLK'event and CLK = '1' then
if starbit='1' then
parity <= '0';
elsif d_in ='1' and stopbit ='0' then
parity <= not parity;
end if;
end if;
end process;

d_out <= parity;

uuupppssss ....
probably that's all folks ... )) ???