Dual port block RAM design, help!

[ro888]

I am trying to build a set of dual port block rams under Sparatan 3E environment. However, I got the following message:

ERROR:Xst:2009 - Model 'RAMB16_S1_S4' has different characteristics in destination library. The user component name 'RAMB16_S1_S4' conflicts with the library primitive name 'RAMB16_S1_S4'.
ERROR:Xst:1831 - Missing ports are:DOA0 DIA0 
ERROR:Xst:1832 - Unknown ports are:DOA DIA

Could anybody help me to solve it?

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
----- This uses 5 banks of 16K-bit blocks of dual port RAM
-----  ports A is 1-bit wide, by 16k-bit long (addresses), used for write only
-----  port B is 4-bit wide, by 4kbit long (addresses), used for read only

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity ram_bus is
  port (DataIn_A  : in STD_LOGIC;
        Addr_A    : in STD_LOGIC_VECTOR (16 downto 0);
		  CLK     : in STD_logic;
        DataOut_B : out STD_LOGIC_VECTOR (3 downto 0);
        Addr_B    : in STD_LOGIC_VECTOR (14 downto 0)
       ); 
end ram_bus;

architecture model of ram_bus is

---- signals
signal ENA_0, ENA_1, ENA_2, ENA_3, ENA_4: std_logic;    -- selection of block for port A access
signal DOB_0, DOB_1, DOB_2, DOB_3, DOB_4: std_logic_vector (3 downto 0);    -- data outputs (port B)
signal ENB_0, ENB_1, ENB_2, ENB_3, ENB_4: std_logic;  -- enable bits (port B)
signal ENA_A : std_logic_vector (4 downto 0); --5 bits selection for Part A


----- The block RAM is defined using component instantiation


component RAMB16_S1_S4

  generic (
       WRITE_MODE_A : string := "WRITE_FIRST";
       WRITE_MODE_B : string := "WRITE_FIRST";
       INIT_A : bit_vector  := X"0";
       SRVAL_A : bit_vector  := X"0";
       INIT_B : bit_vector  := X"0";
       SRVAL_B : bit_vector  := X"0"
	);	

  port (DIA    : in STD_LOGIC;
        DIB    : in STD_LOGIC_VECTOR (3 downto 0);
        ENA    : in STD_logic;
        ENB    : in STD_logic;
        WEA    : in STD_logic;
        WEB    : in STD_logic;
        SSRA   : in STD_logic;		--Port A Synchronous Set/Reset Input
        SSRB   : in STD_logic;		--Port B Synchronous Set/Reset Input
        CLKA   : in STD_logic;
        CLKB   : in STD_logic;
        ADDRA  : in STD_LOGIC_VECTOR (13 downto 0);	-- Port A 14-bit Address Input
        ADDRB  : in STD_LOGIC_VECTOR (11 downto 0);	-- Port B 12-bit Address Input
        DOA    : out STD_LOGIC;								-- Port A 1-bit Data Output
        DOB    : out STD_LOGIC_VECTOR (3 downto 0)		-- Port B 4-bit Data Output

       ); 
end component;


-- the architecture consists of component instatiations for block RAM, 
-- i.e. expressed in a 'structural' style, plus address decoders & 
-- multiplexers, described in a 'behavioural' style

begin

-- Component instantiations for two blocks of RAM
-- unused inputs are tied to appropriate logic levels
-- unused outputs are left 'open'
RAM1: RAMB16_S1_S4
port map ( DIA => DataIn_A, DIB => "1111", ENA => ENA_0, ENB => ENB_0,
           WEA => '1', WEB => '0', SSRA => '0', SSRB => '0',
           CLKA => CLK, CLKB => CLK, ADDRA => Addr_A(13 downto 0), ADDRB => Addr_B(11 downto 0),
           DOA => OPEN, DOB => DOB_0 );

RAM2: RAMB16_S1_S4
port map ( DIA => DataIn_A, DIB => "1111", ENA => ENA_1, ENB => ENB_1,
           WEA => '1', WEB => '0', SSRA => '0', SSRB => '0',
           CLKA => CLK, CLKB => CLK, ADDRA => Addr_A(13 downto 0), ADDRB => Addr_B(11 downto 0),
           DOA => OPEN, DOB => DOB_1 );

RAM3: RAMB16_S1_S4
port map ( DIA => DataIn_A, DIB => "1111", ENA => ENA_2, ENB => ENB_2,
           WEA => '1', WEB => '0', SSRA => '0', SSRB => '0',
           CLKA => CLK, CLKB => CLK, ADDRA => Addr_A(13 downto 0), ADDRB => Addr_B(11 downto 0),
           DOA => OPEN, DOB => DOB_2 );
			  
RAM4: RAMB16_S1_S4
port map ( DIA => DataIn_A, DIB => "1111", ENA => ENA_3, ENB => ENB_3,
           WEA => '1', WEB => '0', SSRA => '0', SSRB => '0',
           CLKA => CLK, CLKB => CLK, ADDRA => Addr_A(13 downto 0), ADDRB => Addr_B(11 downto 0),
           DOA => OPEN, DOB => DOB_3 );
			  
RAM5: RAMB16_S1_S4
port map ( DIA => DataIn_A, DIB => "1111", ENA => ENA_4, ENB => ENB_4,
           WEA => '1', WEB => '0', SSRA => '0', SSRB => '0',
           CLKA => CLK, CLKB => CLK, ADDRA => Addr_A(13 downto 0), ADDRB => Addr_B(11 downto 0),
           DOA => OPEN, DOB => DOB_4 );
			  
--Port B enable bits are all set to '1'
ENB_0 <= '1';	
ENB_1 <= '1';
ENB_2 <= '1';
ENB_3 <= '1';
ENB_4 <= '1';

-- mux output - to select right memory bank from port A 

ENA_0 <= ENA_A (0);
ENA_1 <= ENA_A (1);
ENA_2 <= ENA_A (2);
ENA_3 <= ENA_A (3);
ENA_4 <= ENA_A (4);


with Addr_A (16 DOWNTO 14) select
	  ENA_A <= "00001" when "000",
					  "00010" when "001",
					  "00100" when "010",
					  "01000" when "011",
					  "10000" when "100",
	  (others => 'X') when others;   


-- mux output - port B 
-- selects data output from one of the blocks, depending on the address
with Addr_B (14 DOWNTO 12) select
	  DataOut_B <= DOB_0 when "000",
					   DOB_1 when "001",
						DOB_2 when "010",
						DOB_3 when "011",
						DOB_4 when "100",
		    (others => 'X') when others;   

end model;

 

[blacktom]

ro888,

ERROR:Xst:1831 - Missing ports areOA0 DIA0
ERROR:Xst:1832 - Unknown ports areOA DIA

Maybe it helps when you change the signals DOA to DOA0
and DIA to DIA0 ?

Blacktom