I am having trouble implimenting my display driver for my dice game Kraps. I have to multiplex to be able to display two different values on the 7 segment display. One value is point and the other is score. The other two digits display the dice roll. I have included the VHDL code for anyone to view. Any help on this matter would greatly be appreciated.
Thanks,
Anaki73
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DisplayDriver is
Port ( Play : in STD_LOGIC;
clk: in STD_LOGIC;
die1 : in STD_LOGIC_VECTOR (3 downto 0);
die2 : in STD_LOGIC_VECTOR (3 downto 0);
Point : in STD_LOGIC_Vector (3 downto 0);
PointValid : in STD_LOGIC;
Score : in STD_LOGIC_VECTOR (7 downto 0);
Hz1000 : in STD_LOGIC;
Anode : out STD_LOGIC_VECTOR (3 downto 0);
Cathode: out STD_LOGIC_VECTOR (7 downto 0));
end DisplayDriver;
architecture Behavioral of DisplayDriver is
signal count:STD_LOGIC_VECTOR (1 downto 0):= "00" ;
signal Cat: STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal muxout:STD_LOGIC_VECTOR (3 downto 0):="0000";
signal Bcd0:STD_LOGIC_VECTOR (3 downto 0);
signal Bcd1:STD_LOGIC_VECTOR (3 downto 0);
signal Bcd2:STD_LOGIC_VECTOR (3 downto 0);
signal Bcd3:STD_LOGIC_VECTOR (3 downto 0);
signal PointA:STD_LOGIC_VECTOR (3 downto 0);
signal PointB:STD_LOGIC_VECTOR (3 downto 0);
signal ScoreA:STD_LOGIC_VECTOR (3 downto 0);
signal ScoreB:STD_LOGIC_VECTOR (3 downto 0);
--two bit counter to cycle through the multiplexer and decoder
begin
process (clk) begin
if rising_edge (clk)then
if Hz1000='1' then
count <=count +1;
else count <=count;
end if;
end if;
end process;
--1 of 4 decoder
process (count, Bcd0, Bcd1, Bcd2, Bcd3) begin
case count is
when "00" => Anode <="1110";
muxout <= Bcd0;
when "01" => Anode <="1101";
muxout <= Bcd1;
when "10" => Anode <="1011";
muxout <=Bcd2;
when "11" => Anode <="0111";
muxout <= Bcd3;
when others => Anode <= "1111";
end case;
end process;
process (muxout) begin --impliments the Bcd to 7 segment encoder
-- which drives segment display
case muxout is
when "0000" => Cat <="11000000";
when "0001" => Cat <="11111001";
when "0010" => Cat <="10100100";
when "0011" => Cat <="10110000";
when "0100" => Cat <="10011001";
when "0101" => Cat <="10010010";
when "0110" => Cat <="10000010";
when "0111" => Cat <="11111000";
when "1000" => Cat <="10000000";
when "1001" => Cat <="10010000";
when "1010" => Cat <="11111111";
when others => Cat <="11111111";
end case;
end process;
Cathode<=Cat;
--This process seperates the score and point values into seperate digit values
PointA<="0001" when Point > 9 else "0000";
PointB <= Point when Point < 9 else "0000";
Bcd0 <=die1;
Bcd1 <=die2;
Bcd2 <= "0000" when PointValid ='0' and play='0'
else "1010" when PointValid ='0' and play='1'
else "0001" when PointValid='1' and play='0'
else "0010" ;
Bcd3 <= "0000" when PointValid ='0' and play='0'
else "1010" when PointValid ='0' and play='1'
else "0001" when PointValid='1' and play='0'
else "0010" ;
end behavioral;
Thanks,
Anaki73
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DisplayDriver is
Port ( Play : in STD_LOGIC;
clk: in STD_LOGIC;
die1 : in STD_LOGIC_VECTOR (3 downto 0);
die2 : in STD_LOGIC_VECTOR (3 downto 0);
Point : in STD_LOGIC_Vector (3 downto 0);
PointValid : in STD_LOGIC;
Score : in STD_LOGIC_VECTOR (7 downto 0);
Hz1000 : in STD_LOGIC;
Anode : out STD_LOGIC_VECTOR (3 downto 0);
Cathode: out STD_LOGIC_VECTOR (7 downto 0));
end DisplayDriver;
architecture Behavioral of DisplayDriver is
signal count:STD_LOGIC_VECTOR (1 downto 0):= "00" ;
signal Cat: STD_LOGIC_VECTOR (7 downto 0):="00000000";
signal muxout:STD_LOGIC_VECTOR (3 downto 0):="0000";
signal Bcd0:STD_LOGIC_VECTOR (3 downto 0);
signal Bcd1:STD_LOGIC_VECTOR (3 downto 0);
signal Bcd2:STD_LOGIC_VECTOR (3 downto 0);
signal Bcd3:STD_LOGIC_VECTOR (3 downto 0);
signal PointA:STD_LOGIC_VECTOR (3 downto 0);
signal PointB:STD_LOGIC_VECTOR (3 downto 0);
signal ScoreA:STD_LOGIC_VECTOR (3 downto 0);
signal ScoreB:STD_LOGIC_VECTOR (3 downto 0);
--two bit counter to cycle through the multiplexer and decoder
begin
process (clk) begin
if rising_edge (clk)then
if Hz1000='1' then
count <=count +1;
else count <=count;
end if;
end if;
end process;
--1 of 4 decoder
process (count, Bcd0, Bcd1, Bcd2, Bcd3) begin
case count is
when "00" => Anode <="1110";
muxout <= Bcd0;
when "01" => Anode <="1101";
muxout <= Bcd1;
when "10" => Anode <="1011";
muxout <=Bcd2;
when "11" => Anode <="0111";
muxout <= Bcd3;
when others => Anode <= "1111";
end case;
end process;
process (muxout) begin --impliments the Bcd to 7 segment encoder
-- which drives segment display
case muxout is
when "0000" => Cat <="11000000";
when "0001" => Cat <="11111001";
when "0010" => Cat <="10100100";
when "0011" => Cat <="10110000";
when "0100" => Cat <="10011001";
when "0101" => Cat <="10010010";
when "0110" => Cat <="10000010";
when "0111" => Cat <="11111000";
when "1000" => Cat <="10000000";
when "1001" => Cat <="10010000";
when "1010" => Cat <="11111111";
when others => Cat <="11111111";
end case;
end process;
Cathode<=Cat;
--This process seperates the score and point values into seperate digit values
PointA<="0001" when Point > 9 else "0000";
PointB <= Point when Point < 9 else "0000";
Bcd0 <=die1;
Bcd1 <=die2;
Bcd2 <= "0000" when PointValid ='0' and play='0'
else "1010" when PointValid ='0' and play='1'
else "0001" when PointValid='1' and play='0'
else "0010" ;
Bcd3 <= "0000" when PointValid ='0' and play='0'
else "1010" when PointValid ='0' and play='1'
else "0001" when PointValid='1' and play='0'
else "0010" ;
end behavioral;