Debuging a path file

[user4637]

library IEEE;
use IEEE.std_logic_1164.all;

entity datapath is
port (
rst : in std_logic;
clock : in std_logic;
dataIn : in std_logic_vector(7 downto 0);
DA : in std_logic;
inputSelect : in std_logic;
load : in std_logic;
FS : in std_logic_vector(3 downto 0);
N : out std_logic;
Z : out std_logic;
dataOutA : out std_logic_vector(7 downto 0);
dataOutB : out std_logic_vector(7 downto 0)
);


end datapath;

Architecture behavioural of datapath is

component Not_Gate is
port(
I : in STD_LOGIC;
O : out STD_LOGIC
);
end component Not_Gate;

component And_2 is
port(
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
O : out STD_LOGIC
);
end component And_2;

component mux_21_8bit is
port (
in0 : in std_logic_vector(7 downto 0);
in1 : in std_logic_vector(7 downto 0);
outVal : out std_logic_vector(7 downto 0);
sel : in std_logic
);

end component mux_21_8bit;

component Register_8 is
port(
clk : in STD_LOGIC;
enable : in STD_LOGIC;
clear : in STD_LOGIC;
D : in STD_LOGIC_VECTOR(7 downto 0);
Q : out STD_LOGIC_VECTOR(7 downto 0)
-- Qb : out STD_LOGIC_VECTOR(7 downto 0) -- not required, so I removed it
);
end component Register_8;

component ALU is
port(
A : in STD_LOGIC_VECTOR(7 downto 0);
B : in STD_LOGIC_VECTOR(7 downto 0);
funcSel : in STD_LOGIC_VECTOR(3 downto 0);
negative : out STD_LOGIC;
zero : out STD_LOGIC;
G : out STD_LOGIC_VECTOR(7 downto 0)
);
end component ALU;

signal S1, S2, S3: STD_LOGIC;
signal V1, V2, V3, V4: STD_LOGIC_VECTOR(7 downto 0);

begin

Comp_porteNot: Not_Gate port map(
I=>DA,
O=>S1
);

Comp_porteAnd_1: And_2 port map(
I1=>load,
I2=>S1,
O=>S2
);

Comp_porteAnd_2: And_2 port map(
I1=>load,
I2=>DA,
O=>S3
);

Comp_mux: mux_21_8bit port map(
in0=>V4,
in1=>dataIn,
outVal=>V1,
sel=>inputSelect
);

Comp_Registre_A: Register_8 port map(
clk=>clock,
enable=>S2,
clear=>rst,
D=>V1,
Q=>V2
);

Comp_Registre_B: Register_8 port map(
clk=>clock,
enable=>S3,
clear=>rst,
D=>V1,
Q=>V3
);

Comp_ALU: ALU port map(
A=>V2,
B=>V3,
funcSel=>FS,
negative=>N,
zero=>Z,
G=>V4
);

dataOutA<=V2;
dataOutB<=V3;




end architecture behavioural;