CRC32 Code (ethernet)

[Donnie80]

Hi!

Can anyone urgently help me? I need to implement a crc32 check for an ethernet system. Anyone know where i can get the code from in VHDL?

Many thanks

D.

 

[Darshneider]

Here you go, The first code is a CRC checker in VHDL the second is a psudo
random
packet generator with a CRC append. You can just use the part that
calculates teh FCS/CRC
i think it is clearly marked.

-----------------------------------------------------------------------
-- Code Starts here ---------------------------------------------------
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;

ENTITY prp_recieve IS

PORT (
t_clk : IN std_logic;
Reset_n : IN std_logic;
TxDataValid : IN std_logic;
QuadRxData : IN std_logic_vector(3 DOWNTO 0));

END prp_recieve;

ARCHITECTURE behav OF prp_recieve IS

CONSTANT MagicNum : std_logic_vector(31 DOWNTO 0) := x"C704DD7B";
CONSTANT CRCPoly : std_logic_vector(31 DOWNTO 0) := x"04C11DB7";

TYPE state_type IS (Idle,
CRC_Calc,
CRC_Chk);

SIGNAL PRPRec_State : state_type;

SIGNAL BadPacketReg : std_logic_vector(20 DOWNTO 0);
SIGNAL PacketCntReg : std_logic_vector(20 DOWNTO 0);

BEGIN

QuadPumpPrpsRx: PROCESS (t_clk, Reset_n)
VARIABLE QuadCRCReg : std_logic_vector(31 DOWNTO 0);
VARIABLE XorEnCRC : std_logic_vector(31 DOWNTO 1);
BEGIN
IF Reset_n = '0' THEN
QuadCRCReg := (OTHERS => '1');
XorEnCRC := (OTHERS => QuadCRCReg(31));
BadPacketReg <= (OTHERS => '0');
PacketCntReg <= (OTHERS => '0');
ELSIF t_clk'event AND t_clk = '1' THEN
CASE PRPRec_State IS
WHEN Idle =>
QuadCRCReg := (OTHERS => '1');
IF TxDataValid = '1' AND QuadRxData = x&quot;D&quot; THEN
PRPRec_State <= CRC_Calc;
END IF;
WHEN CRC_Calc =>
IF TxDataValid = '1' THEN
-- Calculate the CRC for bit 0
XorEnCRC := (OTHERS => (QuadRxData(0) XOR QuadCRCReg(31)));
QuadCRCReg := (QuadCRCReg(30 DOWNTO 0) XOR
(CRCPoly(31 DOWNTO 1) AND XorEnCRC))
& (QuadRxData(0) XOR QuadCRCReg(31));
-- Calculate the CRC for bit 1
XorEnCRC := (OTHERS => (QuadRxData(1) XOR QuadCRCReg(31)));
QuadCRCReg := (QuadCRCReg(30 DOWNTO 0) XOR
(CRCPoly(31 DOWNTO 1) AND XorEnCRC))
& (QuadRxData(1) XOR QuadCRCReg(31));
-- Calculate the CRC for bit 2
XorEnCRC := (OTHERS => (QuadRxData(2) XOR QuadCRCReg(31)));
QuadCRCReg := (QuadCRCReg(30 DOWNTO 0) XOR
(CRCPoly(31 DOWNTO 1) AND XorEnCRC))
& (QuadRxData(2) XOR QuadCRCReg(31));
-- Calculate the CRC for bit 3
XorEnCRC := (OTHERS => (QuadRxData(3) XOR QuadCRCReg(31)));
QuadCRCReg := (QuadCRCReg(30 DOWNTO 0) XOR
(CRCPoly(31 DOWNTO 1) AND XorEnCRC))
& (QuadRxData(3) XOR QuadCRCReg(31));

ELSE
IF QuadCRCReg /= MagicNum THEN
BadPacketReg <= BadPacketReg + '1';
END IF;
PacketCntReg <= PacketCntReg + '1';
PRPRec_State <= Idle;


END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS QuadPumpPrpsRx;


END behav;
----------------------------------------------------------------------------
--
-- End of Code
----------------------------------------------------------------------------
--


-----------------------------------------------------------------------
-- Code Starts here ---------------------------------------------------
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;


ENTITY prp_generate IS

PORT (
m_clk : IN std_logic;
Reset_n : IN std_logic;
Tx_Packet : IN std_logic;
Rx_Data_Valid : OUT std_logic;
QuadTxData : OUT std_logic_vector(3 DOWNTO 0));

END prp_generate;

ARCHITECTURE behav OF prp_generate IS

----------------------------------------------------------------------------
-
-- Degree 16 Irreducible Polynomial

----------------------------------------------------------------------------
-
CONSTANT PRPSPoly : std_logic_vector(16 DOWNTO 0) := &quot;10111000001101101&quot;;

----------------------------------------------------------------------------
-
CONSTANT CRCPoly : std_logic_vector(31 DOWNTO 0) := x&quot;04C11DB7&quot;;



TYPE state_type IS (Idle,
Time_Delay,
Premble_Gen,
Data_Gen);

SIGNAL PRPGen_State : state_type;

--SIGNAL TimeDelay_Reg : std_logic_vector(14 DOWNTO 0);
SIGNAL TimeDelay_Reg : std_logic_vector(9 DOWNTO 0);
--SIGNAL DelayCount : std_logic_vector(6 DOWNTO 0);
SIGNAL PacketLength_Reg : std_logic_vector(9 DOWNTO 0);
--SIGNAL PacketLgthCnt : std_logic_vector(9 DOWNTO 0);
SIGNAL FCSApndCnt : integer;
SIGNAL PrembleLength : std_logic_vector(3 DOWNTO 0);
----------------------------------------------------------------------------
---
-- Test
----------------------------------------------------------------------------
---
SIGNAL PacketTxCnt : std_logic_vector(3 DOWNTO 0);
----------------------------------------------------------------------------
---
-- Test
----------------------------------------------------------------------------
---
BEGIN

QuadPumpPrbsTx: PROCESS (m_clk, Reset_n)
VARIABLE QuadSftRegTx : std_logic_vector(15 DOWNTO 0);
VARIABLE XorEnTx : std_logic_vector(15 DOWNTO 1);
VARIABLE QuadCRCReg : std_logic_vector(31 DOWNTO 0);
VARIABLE XorEnCRC : std_logic_vector(31 DOWNTO 1);
BEGIN

IF Reset_n = '0' THEN
QuadSftRegTx := (OTHERS => '1');
QuadCRCReg := (OTHERS => '1');
XorEnTx := (OTHERS => QuadSftRegTx(15));
XorEnCRC := (OTHERS => QuadCRCReg(31));
QuadTxData <= QuadSftRegTx(15 DOWNTO 12);

TimeDelay_Reg <= (OTHERS => '0');
--DelayCount <= (OTHERS => '0');
PacketLength_Reg <= (OTHERS => '0');
--PacketLgthCnt <= (OTHERS => '0');
FCSApndCnt <= 8;
PrembleLength <= &quot;1111&quot;;
Rx_Data_Valid <= '0';

--PacketTxCnt <= (OTHERS => '0');
ELSIF m_clk'event AND m_clk = '1' THEN
CASE PRPGen_State IS

-----------------------------------------------------------------------
-- ****************** IDLE ****************

-----------------------------------------------------------------------
WHEN Idle =>
QuadCRCReg := (OTHERS => '1');
--Rx_Data_Valid <= '0';
IF Tx_Packet = '1' THEN

PRPGen_State <= Time_Delay;
--TimeDelay_Reg <= '1' & QuadSftRegTx(15 DOWNTO 2);
TimeDelay_Reg <= QuadSftRegTx(15 DOWNTO 6);

-- Pump the PRPS Generator once to randomize the bits
XorEnTx := (OTHERS => QuadSftRegTx(15));
QuadSftRegTx := (QuadSftRegTx(14 DOWNTO 0) XOR
(PRPSPoly(15 DOWNTO 1) AND XorEnTx))
& QuadSftRegTx(15);
END IF;

-----------------------------------------------------------------------
-- ************** Time Delay **************

-----------------------------------------------------------------------
WHEN Time_Delay =>
IF TimeDelay_Reg /= 0 THEN
TimeDelay_Reg <= TimeDelay_Reg - '1';
ELSE
PRPGen_State <= Premble_Gen;
PacketLength_Reg <= QuadSftRegTx(15 DOWNTO 7) & '0';
--PacketLength_Reg <= &quot;0010000000&quot;;
-- Pump the PRPS Generator once to randomize the bits
XorEnTx := (OTHERS => QuadSftRegTx(15));
QuadSftRegTx := (QuadSftRegTx(14 DOWNTO 0) XOR
(PRPSPoly(15 DOWNTO 1) AND XorEnTx))
& QuadSftRegTx(15);
END IF;


-----------------------------------------------------------------------
-- ************ Premble Gen *************

-----------------------------------------------------------------------
WHEN Premble_Gen =>
Rx_Data_Valid <= '1';
IF PrembleLength /= 1 THEN
PrembleLength <= PrembleLength - '1';
QuadTxData <= &quot;0101&quot;;
ELSE
QuadTxData <= &quot;1101&quot;;
PrembleLength <= &quot;1111&quot;;
PRPGen_State <= Data_Gen;
END IF;

-----------------------------------------------------------------------
-- ************** Data Gen **************

-----------------------------------------------------------------------
WHEN Data_Gen =>
IF PacketLength_Reg /= 0 THEN
PacketLength_Reg <= PacketLength_Reg - '1';

------------------------------------------------------------------
-- This will do 4 calculations of Prbs data in one clock.
-- The MAC Core wants bit 0 first

------------------------------------------------------------------
XorEnTx := (OTHERS => QuadSftRegTx(15));
QuadSftRegTx := (QuadSftRegTx(14 DOWNTO 0) XOR
(PRPSPoly(15 DOWNTO 1) AND XorEnTx))
& QuadSftRegTx(15);
QuadTxData(0) <= QuadSftRegTx(15);

-- Calculate the CRC
XorEnCRC := (OTHERS => (QuadSftRegTx(15) XOR
QuadCRCReg(31)));
QuadCRCReg := (QuadCRCReg(30 DOWNTO 0) XOR
(CRCPoly(31 DOWNTO 1) AND XorEnCRC))
& (QuadSftRegTx(15) XOR QuadCRCReg(31));

XorEnTx := (OTHERS => QuadSftRegTx(15));
QuadSftRegTx := (QuadSftRegTx(14 DOWNTO 0) XOR
(PRPSPoly(15 DOWNTO 1) AND XorEnTx))
& QuadSftRegTx(15);
QuadTxData(1) <= QuadSftRegTx(15);

-- Calculate the CRC
XorEnCRC := (OTHERS => (QuadSftRegTx(15) XOR
QuadCRCReg(31)));
QuadCRCReg := (QuadCRCReg(30 DOWNTO 0) XOR
(CRCPoly(31 DOWNTO 1) AND XorEnCRC))
& (QuadSftRegTx(15) XOR QuadCRCReg(31));

XorEnTx := (OTHERS => QuadSftRegTx(15));
QuadSftRegTx := (QuadSftRegTx(14 DOWNTO 0) XOR
(PRPSPoly(15 DOWNTO 1) AND XorEnTx))
& QuadSftRegTx(15);
QuadTxData(2) <= QuadSftRegTx(15);

-- Calculate the CRC
XorEnCRC := (OTHERS => (QuadSftRegTx(15) XOR
QuadCRCReg(31)));
QuadCRCReg := (QuadCRCReg(30 DOWNTO 0) XOR
(CRCPoly(31 DOWNTO 1) AND XorEnCRC))
& (QuadSftRegTx(15) XOR QuadCRCReg(31));

XorEnTx := (OTHERS => QuadSftRegTx(15));
QuadSftRegTx := (QuadSftRegTx(14 DOWNTO 0) XOR
(PRPSPoly(15 DOWNTO 1) AND XorEnTx))
& QuadSftRegTx(15);
QuadTxData(3) <= QuadSftRegTx(15);

-- Calculate the CRC
XorEnCRC := (OTHERS => (QuadSftRegTx(15) XOR
QuadCRCReg(31)));
QuadCRCReg := (QuadCRCReg(30 DOWNTO 0) XOR
(CRCPoly(31 DOWNTO 1) AND XorEnCRC))
& (QuadSftRegTx(15) XOR QuadCRCReg(31));


-------------------------------------------------------------------
-- Now append FCS/CRC

-------------------------------------------------------------------
ELSIF FCSApndCnt /= 0 THEN
QuadTxData(0) <= NOT QuadCRCReg((FCSApndCnt*4-1));
QuadTxData(1) <= NOT QuadCRCReg((FCSApndCnt*4-2));
QuadTxData(2) <= NOT QuadCRCReg((FCSApndCnt*4-3));
QuadTxData(3) <= NOT QuadCRCReg((FCSApndCnt*4-4));
FCSApndCnt <= FCSApndCnt - 1;
ELSE
FCSApndCnt <= 8;
PRPGen_State <= Idle;
Rx_Data_Valid <= '0';
--PacketTxCnt <= PacketTxCnt + 1;
END IF;

WHEN OTHERS => NULL;
END CASE;


END IF;
END PROCESS QuadPumpPrbsTx;


END behav;
----------------------------------------------------------------------------
--
-- End of Code
----------------------------------------------------------------------------
--

lionel