Counter Pulse

[DVBT]

Good Evening Ladies and Gentlemen,

Just to give you an idea as to what I am doing. I am looking to develop a DVBT system in VHDL. I have developed the majority of the system already. I am just coming to the end of the task, but am looking for some help (sorry if some of its simple stuff but my heads spinning and could do with some assistance!!!)

I'll start with something that will hopefully be simple.
I am looking to design a code that will send a pulse at the output every 12 clock cycles, can anyone think of a simple (reducing hardware uses) approach to this.

Thanks in advance

Dave

 

[ashwin321]

http://en.wikipedia.org/wiki/Linear_feedback_shift_register

USE an 4-bit LSFR and have it reset itself every 12th clock cycle/state.

use the above generated reset pulse as your pulse