convert the clock signal into 50% duty cycle

[spidermanvenom]

Hallo everyone!

Regarding on my project, I'm still doing the design for frame grabber board.
As I have an input clock signal which is greater than 50% duty cycle, I need to convert it into 50% duty cycle. I do not know how to implement it in VHDL program. If someone knows how, please teach me about it. I will appreciate any help from this forum.

Thanks!!!

 

[VHDLguy]

hmmm. A PLL should do the trick. If you don't have one on your FPGA then we will have to think some more. And based on your previous questions and problems I guess its still the same situation....

So,
What are you trying to do with the clock? (Do you really need 50%) What speed is it? and is there a reason it's not 50% duty? Exactly what duty cycle is it?

--

http://www.lateralsands.com/

 

[spidermanvenom]

Thanks Mr. VHDLGuy.....

I appreciate your kindness to answer my/our questions in this forum. Well, I already turnover my project to the higher engineer. They gave me a new project.

Anyway, thanks for your reply....

'til then!.....

 

[VHDLguy]

Sorry to hear that. Well you will have to check out the implementation that they use. Might give you some insight on any bad decisions you made or different ideas you could of had.

--

http://www.lateralsands.com/