Compilation problems

[Finot]

Hello,

(first of all forgive my english)

I just began a University project, I must acquire data from a CMOS CCD sensor and put them in the FPGA memory.

I have big problems with compilation, because it's veeery long, and when it compiled (before I used the "loop" statement), I had problems with the licence:

"Warning: FLEXlm software error: Future license file format or misspelling in license file..."

Do you have advices for me to go back on the right path?

This is the code I use now:



LIBRARY ieee;
Use iEEE.std_logic_1164.all;
Use ieee.std_logic_arith.all;

ENTITY recup IS
PORT(
VSYNC : IN STD_LOGIC;
PCLK : IN STD_LOGIC;
HREF : IN STD_LOGIC;
Y : IN STD_LOGIC_VECTOR (0 TO 7)
);
END recup;

ARCHITECTURE archi OF recup IS
TYPE Matrice is ARRAY (0 TO 639) of std_logic_vector(0 TO 7);
SIGNAL data : Matrice;
SIGNAL i : integer;

BEGIN
PROCESS(PCLK)
BEGIN

LOOP
EXIT WHEN i=1;

IF (VSYNC'EVENT AND VSYNC='0') THEN
IF (PCLK'EVENT AND PCLK='1') THEN
IF HREF='1' THEN
data(i)<=Y;
i<=i+1;
END IF;
END IF;
END IF;

END LOOP;

END PROCESS;
END archi;



Thank you by advance.

 

[Finot]

I hace reveived my NIOS II Evaluation kit, with a FPGA cyclone and SDRAM on the board.
Even if I read the documentation, I really don't have any idea on how to interface the RAM with my card.

Do you have any advice for it?

 

[Finot]

I've got few methods to interface my Cyclone with SDRAM, but the problem is that I can't get any information on the wiring of the board I use (NIOS II development kit)!!

Has anybody already worked with that device?