compass

[johan1981]

Hi,

We have to built a compass in VHDL.

We get a 4 bit code as input. We get for example "0000". This result in N (North) on a 7-segment display. When "0001", this will result in N N E (North North East) on 3 displays.

We don't know how to control the displays.

Can anybody help us?

This is what we have so far:


EASE/HDL begin --------------------------------------------------------
-- Architecture 'a0' of 'decoder'.
-- Skeleton generated by Ease at Tue May 24 12:29:22 2005.
---------------------------------------------------------------------------
-- Copy of the interface declaration of entity 'decoder' :
--
-- port(
-- reset : in std_logic ; -- Reset
-- clk : in std_logic ; -- Clock
-- data_in : in std_logic_Vector(3 downto 0) ;
-- disp1 : out std_logic ;
-- disp2 : out std_logic ;
-- disp3 : out std_logic ;
-- segment : out std_logic_Vector(7 downto 0) ) ;
-- EASE/HDL end ----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity decoder is
port ( clk_disp : in std_logic;
clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (3 downto 0);
--load : IN std_logic;
disp1 : out std_logic;
disp2 : out std_logic;
disp3 : out std_logic;
segment : out std_logic_vector (7 downto 0) -- MSB=dp, g, f, e, .., LSB=a
);
end decoder;

architecture a0 of decoder is
type allowed_seg_status is
(seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg
_g,seg_h);
signal seg_status : allowed_seg_status;
signal toggle : std_logic_vector (2 downto 0);
signal toggle_seg : std_logic_vector (6 downto 0);
signal data_in : std_logic_vector (3 downto 0);
constant low : std_logic := '0';
constant high : std_logic := '1';

begin


d_ff : process (reset, clk)
begin
if (reset=low) then
data_in <= "0000";
elsif (clk=high and clk'event) then
if (load=high) then
data_in <= datain;
end if;
end if;
end process d_ff;

process (clk_disp, reset)
variable seg_status : allowed_seg_status;
begin
if (rese=low) then
seg_status := seg_a;
elsif (clk_disp=high and clk_disp'event) then
case (seg_status) is
when seg a => seg_status := seg_b;
when seg b => seg_status := seg_c;
when seg c => seg_status := seg_d;
when seg d => seg_status := seg_e;
when seg e => seg_status := seg_f;
when seg f => seg_status := seg_g;
when seg g => seg_status := seg_h;
when seg h => seg_status := seg_a;
end case;
end if;
status_seg <= seg_status;
end process;

seg_decoder: process (status_seg)
variable segmenten : std_logic_vector (7 downto 0);
begin
segmenten := "11111111";
case (status_seg) is
when seg_a => segment(0) := not toggle_seg(0);
when seg_b => segment(1) := not toggle_seg(1);
when seg_c => segment(2) := not toggle_seg(2);
when seg_d => segment(3) := not toggle_seg(3);
when seg_e => segment(4) := not toggle_seg(4);
when seg_f => segment(5) := not toggle_seg(5);
when seg_g => segment(6) := not toggle_seg(6);
when seg_h => segment(7) := not toggle_seg(7);
end case;
segment <= segmenten;
end process seg_decoder;

bin_dec: process (toggle)
variable segment : std_logic_vector (6 downto 0);
variable disp1 : out std_logic;
variable disp2 : out std_logic;
variable disp3 : out std_logic;
begin
case (toggle) is
when "0000" => disp1 := '0', segment := "1111111" and
disp2 := '0',and
disp3 := '1', segment := "0110111";

end a0 ; -- of decoder