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Comparison of 2 vhdl designs

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Guest_imported

Guest_imported

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Jan 1, 1970
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Hey!

I am trying to compare the logic of two vhdl designs to check if they are the same.
I have an original file which I modified and extracted things to another component. Now I would like to see if the entire project still has the same logic or I made a mistake somewhere while modifying. Is there a way to compare those two designs without having to write a testbench (design is very complicated)?
 
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