Common top file

[user4637]

library IEEE;
use IEEE.std_logic_1164.all;


entity machine_top is
port(
clock : in STD_LOGIC;
rst : in STD_LOGIC;
IR : out STD_LOGIC_VECTOR(7 downto 0);
PC : out STD_LOGIC_VECTOR(7 downto 0);
RegA : out STD_LOGIC_VECTOR(7 downto 0);
RegB : out STD_LOGIC_VECTOR(7 downto 0);
STOut : out STD_LOGIC_VECTOR(3 downto 0)
);
end machine_top;
architecture machine_top of machine_top is

component controller is
port (
rst : in std_logic;
clock : in std_logic;
N : in std_logic;
Z : in std_logic;
memoryData : in std_logic_vector(7 downto 0);
DA : out std_logic;
inputSelect : out std_logic;
load : out std_logic;
memAddressSelect : out std_logic;
read : out std_logic;
FS : out std_logic_vector(3 downto 0);
PCOut : out std_logic_vector(7 downto 0);
IROut : out std_logic_vector(7 downto 0);
STOut : out std_logic_vector(3 downto 0)
);
end component controller;

signal sig_N, sig_Z, sig_DA, sig_inputSelect, sig_load, sig_memAddressSelect, sig_read: std_logic;
signal sig_PCOut, sig_IROut: std_logic_vector(7 downto 0);
signal sig_FS, sig_STOut: std_logic_vector(3 downto 0);


component datapath is
port (
rst : in std_logic;
clock : in std_logic;
dataIn : in std_logic_vector(7 downto 0);
DA : in std_logic;
inputSelect : in std_logic;
load : in std_logic;
FS : in std_logic_vector(3 downto 0);
N : out std_logic;
Z : out std_logic;
dataOutA : out std_logic_vector(7 downto 0);
dataOutB : out std_logic_vector(7 downto 0)
);
end component datapath;

signal sig_dataOutA,sig_dataOutB: std_logic_vector(7 downto 0);
--signal sig_dataIn: std_logic_vector(7 downto 0);

--bloc_memoire

component memory is
port (
rst : in std_logic; -- signal global
clock : in std_logic; -- signal global
read : in std_logic; -- Signal qui indique la lecture ou ecriture a la
-- memoire: 0 ecrit dans la memoire
-- 1 lit la memoire
address : in std_logic_vector(7 downto 0); -- Addresse de memoire (ecriture ou lecture)
dataIn : in std_logic_vector(7 downto 0); -- Donne d'entree
dataOut : out std_logic_vector(7 downto 0) -- Donne de sortie
);
end component memory;

signal sig_address, sig_dataOut: std_logic_vector(7 downto 0);

--bloc_mux

component mux_21_8bit is
port (
in0 : in std_logic_vector(7 downto 0);
in1 : in std_logic_vector(7 downto 0);
outVal : out std_logic_vector(7 downto 0);
sel : in std_logic
);
end component mux_21_8bit;

--signal sig_in0, sig_in1, sig_outVal: std_logic_vector(7 downto 0);
--signal sig_sel: std_logic;

begin

STOut<=sig_STOut;
RegA<=sig_dataOutA;
RegB<=sig_dataOutB;
PC<=sig_PCOut;
IR<=sig_IROut;

bloc_mux: mux_21_8bit port map(
in0=>sig_PCOut,
in1=>sig_dataOutA,
outVal=>sig_address,
sel=>sig_memAddressSelect
);

bloc_controle: controller port map(
rst=>rst,
clock=>clock,
N=>sig_N,
Z=>sig_Z,
memoryData=>sig_dataOut,
DA=>sig_DA,
inputSelect=>sig_inputSelect,
load=>sig_load,
memAddressSelect=>sig_memAddressSelect,
read=>sig_read,
FS=>sig_FS,
PCOut=>sig_PCOut,
IROut=>sig_IROut,
STOut=>sig_STOut
);

bloc_traitement: datapath port map (
rst=>rst,
clock=>clock,
dataIn=>sig_dataOut,
DA=>sig_DA,
inputSelect=>sig_inputSelect,
load=>sig_load,
FS=>sig_FS,
N=>sig_N,
Z=>sig_Z,
dataOutA=>sig_dataOutA,
dataOutB=>sig_dataOutB
);

bloc_memoire: memory port map (
rst=>rst,
clock=>clock,
read=>sig_read,
address=>sig_address,
dataIn=>sig_dataOutB,
dataOut=>sig_dataOut
);

end machine_top;