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Clock
- Thread starter lbh12456
- Start date
You can´t have a "clock" without one osclilator...
If you are using VHDL for Behavioral simulation
entity clk_2MHz is
Port (clk_2MHz : out std_logic
);
end clk_2Mz;
architecture Behavioral of clk_2k is
signal clk : std_logic := '0';
begin
clk <= not clk after 250 ns;
process(clk)
begin
clk_2MHz <= clk;
end process;
end Behavioral;
note that you can't implement because after
If you are using VHDL for Behavioral simulation
entity clk_2MHz is
Port (clk_2MHz : out std_logic
);
end clk_2Mz;
architecture Behavioral of clk_2k is
signal clk : std_logic := '0';
begin
clk <= not clk after 250 ns;
process(clk)
begin
clk_2MHz <= clk;
end process;
end Behavioral;
note that you can't implement because after
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