Clock Multiplier

[Oppenheimer]

Hi All,

I wanna ask something about creating different clock frequencies. Basicly I have 48 Mhz clock signal on my CPLD board. But I need lower frequencies (about 100Hz) to scan more than one seven segment display. I have used different code styles but could not get the signals. "Loop", "after" statements do not respond on the simulation. What can be the reason? What is the correct usage of after statement?
Any suggestion?

Thanks,
oppenheimer

 

[jeandelfrigo]

Hello Oppenheimer,

Are you only trying to implement this in simulation or do you really want to synthesize the code?

The thing is you talk about a CPLD, now a CPLD is de facto something with few flip flops. And the basic way to do clock division is using flipflops.

If you use a simple FPGA or CPLD you only have the basic logic elements that you can use.

So clock division is done by using a counter.

Lets say you have a 48MHz clock and you want to make a 3MHz clock (this is divided by 16). The you use a 4 bit counter. That counts continuously at the 48MHz clock. You use the highest bit as the output clock signal and thus you have a sixteen times lower clock with 50%duty cycle.

This of course only works for divisions where the divider is a multiple of 2. You could alllways write a more complex autoressetting counter to create clocks that use other than binary dividers.

Some downsides:

This eats up flipflops, especially for high divisions. And CPLDs do not have those in big numbers.

When you want to use the generated clock to drive performant logic in chip or on board you can run into timing issues.

Stability is not so good certainly over temperature.

That is why FPGA manufacturers use DLL (DCM Xilinx) and PLL (Altera and Xilinx V5) as separate hardware components to make life easier.

Altera even has some basic clockgeneration component in its MaxII cplds.

So the only advise I can give you further is:

Try using a lower clock to start from, this reduces the flip flops you need.

Try to target for a good part (MaxII or FPGA)


regards

jeandelfrigo