Clock help

[sheenjrg]

Hey guys I need to generate a signal that is low for 8 clk cycles and then high for 8 clk cycles. Which is the shortest way to code for this.

 

[VHDLguy]

Use a 3 bit counter.

here is a sync reset version of the code (just cause i prefer sync reset rather than async, no other reason), same reason goes for my use of unsigned rather than std_logic_vector and signals rather than variables.


-- signal declarations
signal count : unsigned(2 downto 0);
signal hi8low8 : std_logic;

[... snip ...]

process
begin
wait until clock'event and clock= '1';
if reset = '1' then
count <= &quot;000&quot;;
hi8low8 <= '0';
else
-- unsigned signal will roll over when it gets to
-- &quot;111&quot;
count <= count + 1;

if count = unsigned'(&quot;111&quot then
hi8low8 <= not hi8low8;
end if;
end if;
end process;

this of course assumes that clock and reset are also declared (in this case in a port declaration to this entity). I didn't include any of the entity/architecture declarations etc.

Of course you could write this lots of ways.

 

[sheenjrg]

Yes I tried that but I don't know why it didn't work.

What I earlier tried was

wait until clk' event and clk ='1';
if rst = '1'then
count <= &quot;000&quot;;
DSP_TOSC_INTV <= '0';
DSP_RESET <= '0';
else

count <= count + 1;
if count = &quot;111&quot; then
DSP_RESET <= not DSP_RESET;
end if;
end if;

end process;

 

[VHDLguy]

What was the problem with this code? Seems ok to me.

Any error messages or other info?

 

[sheenjrg]

No its ok I got it. my bad I didn't define reset.

Thanks a lot dude.