Hi all
I am very new to VHDL
I am trying to write a simple program, and when i run the Behavioral simulation it all looks good, and i perform the way it should...
but i dont get any result when i run the Post-Fit simulation.
these are the errors i get:
ERROR:Simulator:37 - Sdf root module /UUT/ specified does not exist in the
and this is the Warnings:
WARNING:HDLParsers:3583 - File "N:/J.30/env/TOS/HDLPkgs/vhdl/vital2000/restricted/timing_b.vhd" which file "C:/Xilinx91i/vhdl/src/simprims/simprim_Vcomponents.vhd" depends on is modified, but has not been compiled. You may need to compile "N:/J.30/env/TOS/HDLPkgs/vhdl/vital2000/restricted/timing_b.vhd" first.
WARNING:Simulator:273 - Default port map for entity sds to component sds connects OUT mode local port StepMotorA of the component to INOUT mode port of the entity.
WARNING:Simulator:273 - Default port map for entity sds to component sds connects OUT mode local port StepMotorB of the component to INOUT mode port of the entity.
WARNING:Simulator:425 - No default binding for component sds. Port Frem is not on the entity.
WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst test1/UUT
WARNING:Simulator:144 - Cannot find block UUT/.
this is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sds is
Port ( Frem, Tilbage, clock : in STD_LOGIC;
Q : inout std_logic_vector(1 downto 0) := "00";
C : inout std_logic := '1';
StepMotorA, StepMotorB : out STD_LOGIC);
end sds;
architecture Behavioral of sds is
begin
state : process(clock) is
begin
if clock'event and clock = '1' then
C <= not(C);
if (C = '0') then Q(0) <= not(Q(0)); end if;
if (C = '1') then Q(1) <= not(Q(1)); end if;
end if;
end process state;
StepMotorA <= Q(0);
StepMotorB <= Q(1);
end Behavioral;
btw. the chip i want to program is a CX9536
many thanks
Andreas Nordbek
I am very new to VHDL
I am trying to write a simple program, and when i run the Behavioral simulation it all looks good, and i perform the way it should...
but i dont get any result when i run the Post-Fit simulation.
these are the errors i get:
ERROR:Simulator:37 - Sdf root module /UUT/ specified does not exist in the
and this is the Warnings:
WARNING:HDLParsers:3583 - File "N:/J.30/env/TOS/HDLPkgs/vhdl/vital2000/restricted/timing_b.vhd" which file "C:/Xilinx91i/vhdl/src/simprims/simprim_Vcomponents.vhd" depends on is modified, but has not been compiled. You may need to compile "N:/J.30/env/TOS/HDLPkgs/vhdl/vital2000/restricted/timing_b.vhd" first.
WARNING:Simulator:273 - Default port map for entity sds to component sds connects OUT mode local port StepMotorA of the component to INOUT mode port of the entity.
WARNING:Simulator:273 - Default port map for entity sds to component sds connects OUT mode local port StepMotorB of the component to INOUT mode port of the entity.
WARNING:Simulator:425 - No default binding for component sds. Port Frem is not on the entity.
WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst test1/UUT
WARNING:Simulator:144 - Cannot find block UUT/.
this is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sds is
Port ( Frem, Tilbage, clock : in STD_LOGIC;
Q : inout std_logic_vector(1 downto 0) := "00";
C : inout std_logic := '1';
StepMotorA, StepMotorB : out STD_LOGIC);
end sds;
architecture Behavioral of sds is
begin
state : process(clock) is
begin
if clock'event and clock = '1' then
C <= not(C);
if (C = '0') then Q(0) <= not(Q(0)); end if;
if (C = '1') then Q(1) <= not(Q(1)); end if;
end if;
end process state;
StepMotorA <= Q(0);
StepMotorB <= Q(1);
end Behavioral;
btw. the chip i want to program is a CX9536
many thanks
Andreas Nordbek