can any one please help me my dead line is next week

[madapati12345]

I have to design a micro controller bus interface with read write, chip select ,8 bit bi directional data and having one address.This need to be interlinked with SPI.


library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mc_interface is
port(
addr:in std_logic_vector(1 downto 0);
data:in std_logic_vector(7 downto 0);
rd:in std_logic;
wr : in std_logic;
sys_clk:in std_logic;
rst:in std_logic;
cs:in std_logic;
xmit_empty : in std_logic;
rcv_full : in std_logic;
spierr : in std_logic;
rxddata:in std_logic_vector(7 downto 0);
tranreg,rcvreg,statreg,ctrlreg,data_out:inout std_logic_vector(7 downto 0));
end mc_interface;


architecture mc_interface of mc_interface is

signal xmit_empty_reset,rcv_full_reset,spierr_reset:std_logic;
begin
process(sys_clk,rst)
begin
if(rst='1')then

tranreg<= (others => '0');
rcvreg<=(others => '0');
statreg<=(others => '0');
ctrlreg<=(others => '0');
data_out<=(others => '0');
elsif(sys_clk'event and sys_clk='1')then
case addr is
when "00"=>
if(wr='0')then
tranreg<=data;
end if;
if (rd='0')then
data_out<=tranreg;
end if;
when "01"=>
if(wr='0')then
ctrlreg<=data;

end if;
if (rd='0')then
data_out<=ctrlreg;
end if;

when "10"=>
if(wr='0')then
rcvreg<=rxddata;
end if;
if (rd='0')then
data_out<=rcvreg;
end if;
when "11"=>
if (rd='0')then
statreg <= xmit_empty & rcv_full & spierr & "00000";
data_out<=statreg;
end if;
when others =>
xmit_empty_reset<= '1';
rcv_full_reset <= '1';
spierr_reset <= '1';
end case;
end if;
end process;



end mc_interface;