bidirectional port

[superosjecaj]

Hi!

I'd laike to make a bidirectional port with vhdl, bu i don't know how to...
i tried sth like this
io : inout std_logic;
i : in std logic;
o : std_logic;
rw,vma : in std_logic
...

p0rocess(vma,rw...)
begin
if vma = '1' then
if rw = '1' then
i <= io;
else
io <= o;
end if;
else
io <= 'Z';
end if;
end process;
...

but the synthesis reports a latch...
how can i avoid that

thanx,
blaz

 

[RVSachin]

Latch will be generated when there are incomplete IF-ELSE, CASE, WHEN-ELSE statements in the code. If you want to avoid latches being generated, then, see that the code has the default (ELSE) clause assigned.

Also, can you provide the complete code?
I tried to build a code from the snippet you have given, but was not sure if it was same as whatever you are using.