bidirectional mux/demux?? help

[kn1ghtx]

Hi guys,

I need to create a bidirectional mux in combinational logic only (no flops/latches)... any idea how...??
I've tried this, but this gives me flops...

What I'm trying is, just by reading or writing to the IO, it will automatically read from the in(s) or write to the out(s)...

thanks

entity bi_d_mux is
port ( in1 : in std_logic_vector(n-1 downto 0);
in2 : in std_logic_vector(n-1 downto 0);
out1 : out std_logic_vector(n-1 downto 0);
out2 : out std_logic_vector(n-1 downto 0);
S : in std_logic_vector(1 downto 0);
IO : inout std_logic_vector(n-1 downto 0)
);
end bi_d_mux;

architecture simple of bi_d_mux is
begin
process(S, IO, in1, in2)
begin
case S is
when "00" => IO <= in1;
when "01" => IO <= in2;
when "10" => out1 <= IO;
when "11" => out2 <= IO;
when others => null;
end case;
end process;

 

[jeandelfrigo]

kn1ghtx,

It's kind of logical that your code infers flops.

When S is "10" or "11" what is the value of the output part of IO???
And also :

What is the value of out1 when S = "00" or "01" or "11"?
What is the value of out2 when S = "00" or "01" or "10"?

When you want combinatorical logic every signal or output needs to be declared at any time, if not synthesis will give errors or warning of latches that are inferred.

Try this :

architecture simple of bi_d_mux is
begin
process(S, IO, in1, in2)
begin
IO <= (others => 'Z');
out1 <= (others => '0');
out2 <= (others => '0');
case S is
when "00" => IO <= in1;
when "01" => IO <= in2;
when "10" => out1 <= IO;
when "11" => out2 <= IO;
when others => null;
end case;
end process;

The lines I added make sure that the signals or outputs are allways assigned.

Best Regards

Jeandelfrigo